| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600RegisterInfo.cpp | 1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
11 /// R600 implementation of the TargetRegisterInfo class.
38 reserveRegisterTuples(Reserved, R600::ZERO);
39 reserveRegisterTuples(Reserved, R600::HALF);
40 reserveRegisterTuples(Reserved, R600::ONE);
41 reserveRegisterTuples(Reserved, R600::ONE_INT);
42 reserveRegisterTuples(Reserved, R600::NEG_HALF);
43 reserveRegisterTuples(Reserved, R600::NEG_ONE);
44 reserveRegisterTuples(Reserved, R600::PV_X);
45 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X)
[all...] |
| R600InstrInfo.cpp | 1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
11 /// R600 Implementation of TargetInstrInfo.
67 if ((R600::R600_Reg128RegClass.contains(DestReg) ||
68 R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
69 (R600::R600_Reg128RegClass.contains(SrcReg) ||
70 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) {
72 } else if((R600::R600_Reg64RegClass.contains(DestReg) ||
73 R600::R600_Reg64VerticalRegClass.contains(DestReg)) &&
74 (R600::R600_Reg64RegClass.contains(SrcReg) ||
75 R600::R600_Reg64VerticalRegClass.contains(SrcReg)))
[all...] |
| R600ExpandSpecialInstrs.cpp | 36 #define DEBUG_TYPE "r600-expand-special-instrs"
55 return "R600 Expand special instructions pass";
62 "R600 Expand Special Instrs", false, false)
99 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
103 DstOp.getReg(), R600::OQAP);
104 DstOp.setReg(R600::OQAP);
106 R600::OpName::pred_sel);
108 R600::OpName::pred_sel);
117 case R600::PRED_X: {
125 R600::ZERO); // src
[all...] |
| R600ClauseMergePass.cpp | 37 case R600::CF_ALU:
38 case R600::CF_ALU_PUSH_BEFORE:
77 "R600 Clause Merge", false, false)
79 "R600 Clause Merge", false, false)
88 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT))
95 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled))
101 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT);
120 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT)
[all...] |
| R600EmitClauseMarkers.cpp | 11 /// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
55 case R600::INTERP_PAIR_XY:
56 case R600::INTERP_PAIR_ZW:
57 case R600::INTERP_VEC_LOAD:
58 case R600::DOT_4:
60 case R600::KILL:
80 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
92 case R600::PRED_X:
93 case R600::INTERP_PAIR_XY:
94 case R600::INTERP_PAIR_ZW
[all...] |
| R600MachineScheduler.cpp | 1 //===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===//
11 /// R600 Machine Scheduler interface
165 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
184 if (MI->getOpcode() != R600::COPY)
227 case R600::PRED_X:
229 case R600::INTERP_PAIR_XY:
230 case R600::INTERP_PAIR_ZW:
231 case R600::INTERP_VEC_LOAD:
232 case R600::DOT_4:
234 case R600::COPY
[all...] |
| R600ControlFlowFinalizer.cpp | 97 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() &&
106 case R600::CF_ALU_PUSH_BEFORE:
107 case R600::CF_ALU_ELSE_AFTER:
108 case R600::CF_ALU_BREAK:
109 case R600::CF_ALU_CONTINUE:
171 case R600::CF_PUSH_EG:
172 case R600::CF_ALU_PUSH_BEFORE:
243 case R600::KILL:
244 case R600::RETURN:
256 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600
[all...] |
| R600Packetizer.cpp | 11 /// This pass implements instructions packetization for R600. It unsets isLast
51 StringRef getPassName() const override { return "R600 Packetizer"; }
87 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write);
90 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst);
96 Result[Dst] = R600::PS;
99 if (BI->getOpcode() == R600::DOT4_r600 ||
100 BI->getOpcode() == R600::DOT4_eg) {
101 Result[Dst] = R600::PV_X;
104 if (Dst == R600::OQAP) {
110 PVReg = R600::PV_X
[all...] |
| R600ISelLowering.cpp | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
11 /// Custom DAG lowering for R600
58 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
59 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
60 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
61 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass);
62 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass);
63 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass);
227 // need it for R600.
250 // need it for R600
[all...] |
| AMDILCFGStructurizer.cpp | 435 if (I->getOpcode() == R600::PRED_X) {
437 case R600::PRED_SETE_INT:
438 I->getOperand(2).setImm(R600::PRED_SETNE_INT);
440 case R600::PRED_SETNE_INT:
441 I->getOperand(2).setImm(R600::PRED_SETE_INT);
443 case R600::PRED_SETE:
444 I->getOperand(2).setImm(R600::PRED_SETNE);
446 case R600::PRED_SETNE:
447 I->getOperand(2).setImm(R600::PRED_SETE);
516 case R600::JUMP_COND
[all...] |
| R600OptimizeVectorRegisters.cpp | 82 assert(MI->getOpcode() == R600::REG_SEQUENCE);
140 return "R600 Vector Registers Merge Pass";
149 "R600 Vector Reg Merger", false, false)
151 "R600 Vector Reg Merger", false, false)
162 case R600::R600_ExportSwz:
163 case R600::EG_ExportSwz:
216 unsigned DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass);
221 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG),
237 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
357 if (MI.getOpcode() != R600::REG_SEQUENCE)
[all...] |
| R600AsmPrinter.cpp | 1 //===-- R600AsmPrinter.cpp - R600 Assebly printer ------------------------===//
42 return "R600 Assembly Printer";
54 if (MI.getOpcode() == R600::KILLGT)
82 // R600 / R700
|
| /external/llvm/lib/Target/AMDGPU/TargetInfo/ |
| AMDGPUTargetInfo.cpp | 20 /// be deprecated and there will be a R600 target and a GCN target.
27 RegisterTarget<Triple::r600, false>
28 R600(TheAMDGPUTarget, "r600", "AMD GPUs HD2XXX-HD6XXX");
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/TargetInfo/ |
| AMDGPUTargetInfo.cpp | 20 /// be deprecated and there will be a R600 target and a GCN target.
33 RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600",
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
12 /// The R600 code emitter produces machine code that can be executed
106 if (MI.getOpcode() == R600::RETURN ||
107 MI.getOpcode() == R600::FETCH_CLAUSE ||
108 MI.getOpcode() == R600::ALU_CLAUSE ||
109 MI.getOpcode() == R600::BUNDLE ||
110 MI.getOpcode() == R600::KILL) {
115 if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) {
148 if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) &&
185 // Each R600 literal instruction has two operand
[all...] |
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| sb_context.cpp | 98 TRANSLATE_HW_CLASS(R600);
112 TRANSLATE_CHIP(R600);
|
| sb_core.cpp | 294 TRANSLATE_CHIP(R600);
329 case R600: return HW_CLASS_R600;
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstrInfo.cpp | 96 // FIXME: This should never be called for r600 GPUs.
97 case AMDGPUSubtarget::R600:
|
| AMDGPUSubtarget.cpp | 74 Gen(TT.getArch() == Triple::amdgcn ? SOUTHERN_ISLANDS : R600),
|
| AMDGPUSubtarget.h | 40 R600 = 0,
|
| /external/mesa3d/src/amd/common/ |
| amd_family.h | 105 R600,
|
| /external/mesa3d/include/pci_ids/ |
| r600_pci_ids.h | 1 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
|
| /external/libdrm/radeon/ |
| r600_pci_ids.h | 1 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_hw_context.c | 73 if (ctx->b.chip_class == R600) {
155 (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) {
280 if (ctx->b.chip_class == R600) {
556 if (rctx->b.chip_class == R600)
|
| r600_pipe.c | 161 case R600:
339 /* Supported except the original R600. */
342 /* R600 doesn't support per-MRT blends */
709 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
716 case R600:
737 case R600:
|
