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    Searched refs:REG_DDR3_MR1_OUTBUF_WL_MASK (Results 1 - 2 of 2) sorted by null

  /external/u-boot/drivers/ddr/marvell/axp/
ddr3_write_leveling.c 746 REG_DDR3_MR1_OUTBUF_WL_MASK;
802 REG_DDR3_MR1_OUTBUF_WL_MASK;
840 reg &= REG_DDR3_MR1_OUTBUF_WL_MASK;
983 REG_DDR3_MR1_OUTBUF_WL_MASK;
1034 REG_DDR3_MR1_OUTBUF_WL_MASK;
1072 reg &= REG_DDR3_MR1_OUTBUF_WL_MASK;
    [all...]
ddr3_axp.h 269 #define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */

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