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    Searched refs:REG_PHY_CS_OFFS (Results 1 - 4 of 4) sorted by null

  /external/u-boot/drivers/ddr/marvell/axp/
ddr3_hw_training.c 556 reg |= ((0x4 * cs + mode) << REG_PHY_CS_OFFS);
580 reg |= ((0x4 * cs + mode + 1) << REG_PHY_CS_OFFS);
602 ((0x4 * cs + mode) << REG_PHY_CS_OFFS);
824 reg = (val >> REG_PHY_CS_OFFS) & 0x3F; /*read the phy address */
ddr3_axp.h 309 #define REG_PHY_CS_OFFS 16
ddr3_pbs.c     [all...]
ddr3_write_leveling.c     [all...]

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