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    Searched refs:REG_SDRAM_CONFIG_ADDR (Results 1 - 6 of 6) sorted by null

  /external/u-boot/arch/arm/mach-mvebu/
dram.c 176 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
178 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
206 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
208 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
213 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
224 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
  /external/u-boot/drivers/ddr/marvell/axp/
ddr3_dfs.c 378 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK);
381 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg);
387 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK);
390 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg);
663 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK);
666 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg);
668 reg = reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK;
671 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg);
    [all...]
ddr3_init.c 84 debug_print_reg(REG_SDRAM_CONFIG_ADDR);
473 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
475 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
495 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
643 reg = reg_read(REG_SDRAM_CONFIG_ADDR) &
645 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
661 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
663 reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));
ddr3_hw_training.c 105 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
109 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
114 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
ddr3_axp.h 81 #define REG_SDRAM_CONFIG_ADDR 0x1400
ddr3_spd.c 714 REG_SDRAM_CONFIG_ADDR, REG_SDRAM_CONFIG_ECC_OFFS, 0x1, 0, 0);
758 stat_val = ddr3_get_static_mc_value(REG_SDRAM_CONFIG_ADDR, 0,
776 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
    [all...]

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