| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 67 SmallSet<unsigned, 32>& RegDefs,
71 SmallSet<unsigned, 32>& RegDefs,
79 SmallSet<unsigned, 32> &RegDefs,
129 SmallSet<unsigned, 32> RegDefs;
132 insertDefsUses(slot, RegDefs, RegUses);
157 if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
158 insertDefsUses(FI, RegDefs, RegUses);
172 SmallSet<unsigned, 32> &RegDefs,
206 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
211 if (IsRegInSet(RegDefs, Reg)
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiDelaySlotFiller.cpp | 67 SmallSet<unsigned, 32> &RegDefs,
73 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
149 SmallSet<unsigned, 32> RegDefs;
152 insertDefsUses(Slot, RegDefs, RegUses);
170 if (delayHasHazard(FI, SawLoad, SawStore, RegDefs, RegUses)) {
171 insertDefsUses(FI, RegDefs, RegUses);
181 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
214 if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg))
219 if (isRegInSet(RegDefs, Reg))
226 // Insert Defs and Uses of MI into the sets RegDefs and RegUses
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiDelaySlotFiller.cpp | 67 SmallSet<unsigned, 32> &RegDefs,
73 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
148 SmallSet<unsigned, 32> RegDefs;
151 insertDefsUses(Slot, RegDefs, RegUses);
169 if (delayHasHazard(FI, SawLoad, SawStore, RegDefs, RegUses)) {
170 insertDefsUses(FI, RegDefs, RegUses);
180 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
213 if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg))
218 if (isRegInSet(RegDefs, Reg))
225 // Insert Defs and Uses of MI into the sets RegDefs and RegUses
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 68 SmallSet<unsigned, 32>& RegDefs,
76 SmallSet<unsigned, 32> &RegDefs,
132 SmallSet<unsigned, 32> RegDefs;
155 insertDefsUses(slot, RegDefs, RegUses);
177 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
178 insertDefsUses(I, RegDefs, RegUses);
190 SmallSet<unsigned, 32> &RegDefs,
220 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
225 if (IsRegInSet(RegDefs, Reg))
258 //Insert Defs and Uses of MI into the sets RegDefs and RegUses
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonHazardRecognizer.h | 42 SmallSet<unsigned, 8> RegDefs;
|
| HexagonHazardRecognizer.cpp | 36 RegDefs.clear();
52 if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
88 RegDefs.clear();
118 RegDefs.insert(MO.getReg());
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 71 SmallSet<unsigned, 32>& RegDefs,
75 SmallSet<unsigned, 32>& RegDefs,
83 SmallSet<unsigned, 32> &RegDefs,
173 SmallSet<unsigned, 32> RegDefs;
198 insertCallDefsUses(slot, RegDefs, RegUses);
200 insertDefsUses(slot, RegDefs, RegUses);
220 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
221 insertDefsUses(I, RegDefs, RegUses);
233 SmallSet<unsigned, 32> &RegDefs,
263 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 69 SmallSet<unsigned, 32>& RegDefs,
73 SmallSet<unsigned, 32>& RegDefs,
81 SmallSet<unsigned, 32> &RegDefs,
171 SmallSet<unsigned, 32> RegDefs;
196 insertCallDefsUses(slot, RegDefs, RegUses);
198 insertDefsUses(slot, RegDefs, RegUses);
218 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
219 insertDefsUses(I, RegDefs, RegUses);
231 SmallSet<unsigned, 32> &RegDefs,
261 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| DispatchStage.cpp | 37 SmallVector<unsigned, 4> RegDefs;
40 RegDefs.emplace_back(RegDef->getRegisterID());
42 const unsigned RegisterMask = PRF.isAvailable(RegDefs);
|
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 149 DenseMap<unsigned, MachineInstr *> RegDefs;
208 auto It = RegDefs.find(MO.getReg());
209 if (It == RegDefs.end())
210 RegDefs.insert({MO.getReg(), MI});
233 for (auto &RegDef : RegDefs) {
266 assert((!MO.isDef() || RegDefs.count(MO.getReg())) &&
267 "All defs must be tracked in RegDefs by now!");
268 return !MO.isDef() || RegDefs.find(MO.getReg())->second == MI;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SILoadStoreOptimizer.cpp | 178 DenseSet<unsigned> &RegDefs,
183 RegDefs.insert(Op.getReg());
206 DenseSet<unsigned> &RegDefs,
219 ((Use.readsReg() && RegDefs.count(Use.getReg())) ||
223 addDefsUsesToList(MI, RegDefs, PhysRegUses);
[all...] |
