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    Searched refs:RegResult (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/Target/AArch64/
AArch64CallingConvention.h 115 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
116 if (RegResult) {
118 It.convertToReg(RegResult);
120 ++RegResult;
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
AArch64CallingConvention.h 115 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
116 if (RegResult) {
118 It.convertToReg(RegResult);
120 ++RegResult;
  /external/llvm/lib/Target/ARM/
ARMCallingConv.h 234 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
235 if (RegResult) {
238 It->convertToReg(RegResult);
240 ++RegResult;
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
ARMCallingConv.h 237 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
238 if (RegResult) {
241 It->convertToReg(RegResult);
243 ++RegResult;
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 50 unsigned RegResult = State.AllocateReg(RegList);
51 if (RegResult == AMDGPU::NoRegister)
54 State.addLoc(CCValAssign::getReg(ValNo, ValVT, RegResult, LocVT, LocInfo));
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