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    Searched refs:SET_MEDIUM_FREQ_MASK_BIT (Results 1 - 4 of 4) sorted by null

  /external/u-boot/drivers/ddr/marvell/a38x/
ddr3_training_ip.h 25 #define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
mv_ddr_plat.c 689 SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT |
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ddr3_training.c 80 u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |
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ddr3_debug.c 418 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
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