| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
568 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
571 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
572 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
617 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
619 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
623 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
625 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGAddressAnalysis.cpp | 159 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
171 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
|
| DAGCombiner.cpp | [all...] |
| LegalizeVectorTypes.cpp | 99 case ISD::SIGN_EXTEND:
290 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
464 case ISD::SIGN_EXTEND:
719 case ISD::SIGN_EXTEND:
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
205 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
207 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
209 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 105 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
107 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
113 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
115 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
117 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
119 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
121 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
250 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 300 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
302 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
304 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
306 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
308 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
310 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
312 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
314 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 166 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
168 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
174 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
176 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
178 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
180 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
182 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
311 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 357 // SIGN_EXTEND - Used for integer types, replicating the sign bit
359 SIGN_EXTEND,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 390 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
392 SIGN_EXTEND,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 435 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
437 SIGN_EXTEND,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 323 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom);
452 setTargetDAGCombine(ISD::SIGN_EXTEND);
727 result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 713 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
[all...] |
| LegalizeVectorOps.cpp | 169 case ISD::SIGN_EXTEND:
|
| FastISel.cpp | 274 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
629 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill);
[all...] |
| LegalizeFloatTypes.cpp | 560 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| FunctionLoweringInfo.cpp | 64 // prefer to use SIGN_EXTEND.
78 ExtendKind = ISD::SIGN_EXTEND;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 260 Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
317 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 416 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
589 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 660 // Handle sign_extend and sextload.
661 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
690 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 114 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
591 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 121 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
479 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 242 return ISD::SIGN_EXTEND;
|
