/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 325 SMIN, SMAX, UMIN, UMAX, [all...] |
SelectionDAG.h | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 360 SMIN, SMAX, UMIN, UMAX, [all...] |
TargetLowering.h | [all...] |
/external/llvm/lib/Target/X86/ |
X86IntrinsicsInfo.h | [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 207 case ISD::SMIN: return "smin";
|
LegalizeVectorOps.cpp | 331 case ISD::SMIN: [all...] |
LegalizeIntegerTypes.cpp | 78 case ISD::SMIN: [all...] |
LegalizeVectorTypes.cpp | 114 case ISD::SMIN: 692 case ISD::SMIN: [all...] |
SelectionDAG.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SIISelLowering.cpp | 225 setTargetDAGCombine(ISD::SMIN); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 247 case ISD::SMIN: return "smin"; [all...] |
SelectionDAG.cpp | [all...] |
LegalizeVectorOps.cpp | 390 case ISD::SMIN: [all...] |
LegalizeVectorTypes.cpp | 118 case ISD::SMIN: 749 case ISD::SMIN: [all...] |
LegalizeIntegerTypes.cpp | 80 case ISD::SMIN: [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
ARCISelLowering.cpp | 99 setOperationAction(ISD::SMIN, MVT::i32, Legal);
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIISelLowering.cpp | 402 setOperationAction(ISD::SMIN, MVT::i16, Legal); 561 setOperationAction(ISD::SMIN, MVT::v2i16, Legal); 583 setOperationAction(ISD::SMIN, MVT::v4i16, Custom); 627 setTargetDAGCombine(ISD::SMIN); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 340 setOperationAction(ISD::SMIN, Ty, Legal); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | 605 setOperationAction(ISD::SMIN, VT, Expand); [all...] |
/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 699 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) [all...] |