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  /external/u-boot/arch/arm/mach-exynos/
exynos5_setup.h 473 #define SPLL_CON1_VAL NOT_AVAILABLE
740 #define SPLL_CON1_VAL 0x0020f300
clock_init_exynos5.c 897 writel(SPLL_CON1_VAL, &clk->spll_con1);

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