| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegisterScavenging.cpp | 356 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
359 if (!isAliasUsed(SReg)) {
360 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
361 return SReg;
368 ScavengedReg = SReg;
372 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
376 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
381 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
389 // ScavengedReg = SReg;
392 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
[all...] |
| VirtRegMap.h | 216 /// @brief records virtReg is a split live interval from SReg.
217 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
218 Virt2SplitMap[virtReg] = SReg;
|
| VirtRegRewriter.cpp | 533 unsigned SReg = *SR;
534 if (RegKills[SReg] && KillOps[SReg]->getParent() != &MI)
535 ResurrectConfirmedKill(SReg, TRI, RegKills, KillOps);
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 373 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
376 if (!isRegUsed(SReg)) {
377 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
378 return SReg;
420 Scavenged[SI].Reg = SReg;
424 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
429 TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) +
433 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
441 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
452 // Scavenged[SI].Reg = SReg;
[all...] |
| BranchFolding.cpp | 414 for (MCSuperRegIterator SReg(Reg, TRI); SReg.isValid(); ++SReg) {
415 if (LiveRegs.contains(*SReg)) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 103 unsigned getDPRLaneFromSPR(unsigned SReg);
118 unsigned getPrefSPRLane(unsigned SReg);
147 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
156 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
157 if (!TRI->isVirtualRegister(SReg))
158 return getDPRLaneFromSPR(SReg);
160 MachineInstr *MI = MRI->getVRegDef(SReg);
162 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
169 SReg = MI->getOperand(1).getReg()
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 101 unsigned getDPRLaneFromSPR(unsigned SReg);
116 unsigned getPrefSPRLane(unsigned SReg);
145 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
146 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
154 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
155 if (!TRI->isVirtualRegister(SReg))
156 return getDPRLaneFromSPR(SReg);
158 MachineInstr *MI = MRI->getVRegDef(SReg);
160 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
167 SReg = MI->getOperand(1).getReg()
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| VirtRegMap.h | 137 /// @brief records virtReg is a split live interval from SReg.
138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
139 Virt2SplitMap[virtReg] = SReg;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| VirtRegMap.h | 133 /// records virtReg is a split live interval from SReg.
134 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
135 Virt2SplitMap[virtReg] = SReg;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 268 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
269 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
|
| RegisterScavenging.cpp | 560 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
563 if (!isRegUsed(SReg)) {
564 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
565 return SReg;
568 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
572 << printReg(SReg, TRI) << "\n");
574 return SReg;
660 unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
662 MRI.replaceRegWith(VReg, SReg);
664 return SReg;
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 352 unsigned SReg = Src2->getReg();
353 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
354 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);
357 if (SReg != AMDGPU::VCC)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 454 unsigned SReg = Src2->getReg();
455 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
456 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);
459 if (SReg != AMDGPU::VCC)
|
| SIInstrInfo.cpp | 690 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
691 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
696 .addReg(SReg);
701 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
702 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
708 .addReg(SReg);
712 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
713 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
719 .addReg(SReg);
725 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 596 unsigned SReg;
598 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
600 SReg = PPC::R0;
603 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
605 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
606 .addReg(SReg, RegState::Kill)
627 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | [all...] |
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| MemRegion.h | 415 SubRegion(const MemRegion* sReg, Kind k) : MemRegion(k), superRegion(sReg) {}
476 TypedRegion(const MemRegion* sReg, Kind k) : SubRegion(sReg, k) {}
498 TypedValueRegion(const MemRegion* sReg, Kind k) : TypedRegion(sReg, k) {}
530 CodeTextRegion(const MemRegion *sreg, Kind k) : TypedRegion(sreg, k) {}
544 FunctionCodeRegion(const NamedDecl *fd, const MemRegion* sreg)
545 : CodeTextRegion(sreg, FunctionCodeRegionKind), FD(fd)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
251 OutStreamer.AddComment(Twine(SReg));
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| MemRegion.cpp | 225 ObjCIvarRegion::ObjCIvarRegion(const ObjCIvarDecl *ivd, const MemRegion* sReg)
226 : DeclRegion(ivd, sReg, ObjCIvarRegionKind) {}
333 const MemRegion *sreg) {
336 ID.AddPointer(sreg);
383 const MemRegion *sReg) {
388 ID.AddPointer(sReg);
397 const MemRegion *sReg) {
399 ID.AddPointer(sReg);
409 const MemRegion *SReg) {
412 ID.AddPointer(SReg);
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.cpp | 205 IValueT SReg = EncodedQReg << 2;
206 assert(SReg < RegARM32::getNumSRegs());
207 return SReg;
[all...] |
