/external/libaom/libaom/test/ |
simd_cmp_sse2.cc | 14 #define ARCH SSE2
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simd_sse2_test.cc | 14 #define ARCH SSE2
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comp_avg_pred_test.cc | 57 INSTANTIATE_TEST_CASE_P(SSE2, AV1HighBDDISTWTDCOMPAVGTest, 71 INSTANTIATE_TEST_CASE_P(SSE2, AV1HighBDDISTWTDCOMPAVGUPSAMPLEDTest,
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hiprec_convolve_test.cc | 28 INSTANTIATE_TEST_CASE_P(SSE2, AV1HiprecConvolveTest,
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/external/fec/ |
viterbi27.c | 26 case SSE2: 50 case SSE2: 72 case SSE2: 98 case SSE2: 123 case SSE2: 155 case SSE2:
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viterbi29.c | 26 case SSE2: 50 case SSE2: 72 case SSE2: 98 case SSE2: 123 case SSE2: 148 case SSE2:
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viterbi39.c | 26 case SSE2: 50 case SSE2: 73 case SSE2: 99 case SSE2: 124 case SSE2: 149 case SSE2:
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viterbi615.c | 27 case SSE2: 52 case SSE2: 74 case SSE2: 100 case SSE2: 125 case SSE2: 150 case SSE2:
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cpu_mode_x86.c | 10 "x86 Streaming SIMD Extensions 2 (SSE2)", 23 if(f & (1<<26)){ /* SSE2 is present */ 24 Cpu_mode = SSE2;
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sumsq.c | 31 case SSE2:
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dotprod.c | 40 case SSE2: 61 case SSE2: 83 case SSE2:
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dotprod_sse2_assist.s | 1 # SIMD SSE2 dot product 30 # SSE2 dot product loop unrolled 4 times, crunching 32 terms per loop 58 # SSE2 dot product loop, not unrolled, crunching 4 terms per loop
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peakval.c | 31 case SSE2:
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encode_rs_8.c | 12 static enum {UNKNOWN=0,MMX,SSE,SSE2,ALTIVEC,PORT} cpu_mode; 28 if(f & (1<<26)){ /* SSE2 is present */ 29 cpu_mode = SSE2; 60 case SSE2:
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dtest.c | 19 {"force-sse2",0,NULL,'t'}, 50 Cpu_mode = SSE2;
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sse2bfly29.s | 1 /* Intel SIMD SSE2 implementation of Viterbi ACS butterflies 9 # SSE2 (128-bit integer SIMD) version
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/external/skia/src/core/ |
SkCpu.h | 16 SSE2 = 1 << 1, 66 features |= SSE2; 92 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41); 94 features &= (SkCpu::SSE1 | SkCpu::SSE2);
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/external/skqp/src/core/ |
SkCpu.h | 16 SSE2 = 1 << 1, 66 features |= SSE2; 92 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41); 94 features &= (SkCpu::SSE1 | SkCpu::SSE2);
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/external/libyuv/files/util/ |
Makefile | 3 $(CXX) /arch:SSE2 /Ox /openmp psnr.cc ssim.cc psnr_main.cc
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/external/swiftshader/src/Common/ |
CPUID.hpp | 57 static bool SSE2; 108 return SSE2 && enableSSE2;
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/external/swiftshader/src/Reactor/ |
CPUID.hpp | 52 static bool SSE2; 99 return SSE2 && enableSSE2;
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CPUID.cpp | 35 bool CPUID::SSE2 = detectSSE2(); 204 return SSE2 = (registers[3] & 0x04000000) != 0;
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/external/swiftshader/src/System/ |
CPUID.hpp | 57 static bool SSE2; 108 return SSE2 && enableSSE2;
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/external/tensorflow/tensorflow/core/platform/ |
cpu_info.h | 60 SSE2 = 2,
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cpu_feature_guard.cc | 66 CheckFeatureOrDie(CPUFeature::SSE2, "SSE2"); 116 CheckIfFeatureUnused(CPUFeature::SSE2, "SSE2", missing_instructions);
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