| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonDepTimingClasses.h | 23 case Hexagon::Sched::tc_16d0d8d5:
24 case Hexagon::Sched::tc_1853ea6d:
25 case Hexagon::Sched::tc_60571023:
26 case Hexagon::Sched::tc_7934b9df:
27 case Hexagon::Sched::tc_8fd5f294:
28 case Hexagon::Sched::tc_b9c0b731:
29 case Hexagon::Sched::tc_bcc96cee:
30 case Hexagon::Sched::tc_c6ce9b3f:
31 case Hexagon::Sched::tc_c6ebf8dd:
32 case Hexagon::Sched::tc_c82dc1ff
[all...] |
| /external/perfetto/protos/perfetto/trace_processor/ |
| sched.proto | 22 message Sched {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 24 #define DEBUG_TYPE "pre-RA-sched"
68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
97 case PPC::Sched::IIC_IntDivW:
98 case PPC::Sched::IIC_IntDivD:
99 case PPC::Sched::IIC_LdStLoadUpd:
100 case PPC::Sched::IIC_LdStLDU:
101 case PPC::Sched::IIC_LdStLFDU:
102 case PPC::Sched::IIC_LdStLFDUX:
103 case PPC::Sched::IIC_LdStLHA:
104 case PPC::Sched::IIC_LdStLHAU
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 24 #define DEBUG_TYPE "pre-RA-sched"
68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
97 case PPC::Sched::IIC_IntDivW:
98 case PPC::Sched::IIC_IntDivD:
99 case PPC::Sched::IIC_LdStLoadUpd:
100 case PPC::Sched::IIC_LdStLDU:
101 case PPC::Sched::IIC_LdStLFDU:
102 case PPC::Sched::IIC_LdStLFDUX:
103 case PPC::Sched::IIC_LdStLHA:
104 case PPC::Sched::IIC_LdStLHAU
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| DispatchStage.h | 88 RegisterFile &F, Scheduler &Sched)
90 CarryOver(0U), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 44 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ScheduleDAG.h | 266 Sched::Preference SchedulingPref; // Scheduling preference.
287 SchedulingPref(Sched::None),
301 SchedulingPref(Sched::None),
314 SchedulingPref(Sched::None),
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInstrInfo.cpp | 730 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
731 case Hexagon::Sched::ALU64_tc_2_SLOT23:
732 case Hexagon::Sched::ALU64_tc_3x_SLOT23:
733 case Hexagon::Sched::M_tc_2_SLOT23:
734 case Hexagon::Sched::M_tc_3x_SLOT23:
735 case Hexagon::Sched::S_2op_tc_2_SLOT23:
736 case Hexagon::Sched::S_3op_tc_2_SLOT23:
737 case Hexagon::Sched::S_3op_tc_3x_SLOT23:
|
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 292 Sched::Preference SchedulingPref; // Scheduling preference.
318 SchedulingPref(Sched::None), isDepthCurrent(false),
334 SchedulingPref(Sched::None), isDepthCurrent(false),
349 SchedulingPref(Sched::None), isDepthCurrent(false),
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetMachine.h | 56 namespace Sched {
|
| TargetLowering.h | 189 Sched::Preference getSchedulingPreference() const {
196 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
197 return Sched::None;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 295 Sched::Preference SchedulingPref = Sched::None; ///< Scheduling preference.
|
| TargetLowering.h | 93 namespace Sched {
104 } // end namespace Sched
594 Sched::Preference getSchedulingPreference() const {
601 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
602 return Sched::None;
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 69 namespace Sched {
417 Sched::Preference getSchedulingPreference() const {
424 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
425 return Sched::None;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelLowering.h | 351 Sched::Preference getSchedulingPreference(SDNode *N) const;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 38 #define DEBUG_TYPE "pre-RA-sched"
68 "disable-sched-cycles", cl::Hidden, cl::init(false),
71 // Temporary sched=list-ilp flags until the heuristics are robust.
72 // Some options are also available under sched=list-hybrid.
74 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
75 cl::desc("Disable regpressure priority in sched=list-ilp"));
77 "disable-sched-live-uses", cl::Hidden, cl::init(true),
78 cl::desc("Disable live use priority in sched=list-ilp"));
80 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
83 "disable-sched-physreg-join", cl::Hidden, cl::init(false)
[all...] |
| SelectionDAGISel.cpp | 214 ViewSchedDAGs("view-sched-dags", cl::Hidden,
215 cl::desc("Pop up a window to show sched dags as they are processed"));
242 ISHeuristic("pre-RA-sched",
309 TLI->getSchedulingPreference() == Sched::Source)
311 if (TLI->getSchedulingPreference() == Sched::RegPressure)
313 if (TLI->getSchedulingPreference() == Sched::Hybrid)
315 if (TLI->getSchedulingPreference() == Sched::VLIW)
317 assert(TLI->getSchedulingPreference() == Sched::ILP &&
318 "Unknown sched type!");
[all...] |
| ScheduleDAGSDNodes.cpp | 36 #define DEBUG_TYPE "pre-RA-sched"
44 "sched-high-latency-cycles", cl::Hidden, cl::init(10),
83 SU->SchedulingPref = Sched::None;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 404 Sched::Preference getSchedulingPreference(SDNode *N) const override;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 18 #define DEBUG_TYPE "pre-RA-sched"
70 "disable-sched-cycles", cl::Hidden, cl::init(false),
73 // Temporary sched=list-ilp flags until the heuristics are robust.
74 // Some options are also available under sched=list-hybrid.
76 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
77 cl::desc("Disable regpressure priority in sched=list-ilp"));
79 "disable-sched-live-uses", cl::Hidden, cl::init(true),
80 cl::desc("Disable live use priority in sched=list-ilp"));
82 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
85 "disable-sched-physreg-join", cl::Hidden, cl::init(false)
[all...] |
| SelectionDAGISel.cpp | 100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
128 ISHeuristic("pre-RA-sched",
147 if (TLI.getSchedulingPreference() == Sched::Latency)
149 if (TLI.getSchedulingPreference() == Sched::RegPressure)
151 if (TLI.getSchedulingPreference() == Sched::Hybrid)
153 assert(TLI.getSchedulingPreference() == Sched::ILP &&
154 "Unknown sched type!");
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 63 #define DEBUG_TYPE "pre-RA-sched"
94 "disable-sched-cycles", cl::Hidden, cl::init(false),
97 // Temporary sched=list-ilp flags until the heuristics are robust.
98 // Some options are also available under sched=list-hybrid.
100 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
101 cl::desc("Disable regpressure priority in sched=list-ilp"));
103 "disable-sched-live-uses", cl::Hidden, cl::init(true),
104 cl::desc("Disable live use priority in sched=list-ilp"));
106 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
109 "disable-sched-physreg-join", cl::Hidden, cl::init(false)
[all...] |
| SelectionDAGISel.cpp | 160 ViewSchedDAGs("view-sched-dags", cl::Hidden,
161 cl::desc("Pop up a window to show sched dags as they are processed"));
188 ISHeuristic("pre-RA-sched",
257 TLI->getSchedulingPreference() == Sched::Source)
259 if (TLI->getSchedulingPreference() == Sched::RegPressure)
261 if (TLI->getSchedulingPreference() == Sched::Hybrid)
263 if (TLI->getSchedulingPreference() == Sched::VLIW)
265 assert(TLI->getSchedulingPreference() == Sched::ILP &&
266 "Unknown sched type!");
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 176 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
184 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 181 return (get(Opcode).getSchedClass() == R600::Sched::TransALU);
189 return (get(Opcode).getSchedClass() == R600::Sched::VecALU);
[all...] |
