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    Searched refs:SpilledReg (Results 1 - 6 of 6) sorted by null

  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.h 194 struct SpilledReg {
198 SpilledReg() = default;
199 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
222 DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
229 ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
232 ArrayRef<SpilledReg>() : makeArrayRef(I->second);
SIMachineFunctionInfo.cpp 250 std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
302 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
SIRegisterInfo.cpp 648 ArrayRef<SIMachineFunctionInfo::SpilledReg> VGPRSpills
745 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
826 ArrayRef<SIMachineFunctionInfo::SpilledReg> VGPRSpills
    [all...]
  /external/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.h 123 struct SpilledReg {
126 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
127 SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { }
135 SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
SIMachineFunctionInfo.cpp 184 SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg (
189 return SpilledReg();
202 struct SpilledReg Spill;
SIRegisterInfo.cpp 528 struct SIMachineFunctionInfo::SpilledReg Spill =
592 struct SIMachineFunctionInfo::SpilledReg Spill =
    [all...]

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