| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRInstrInfo.cpp | 56 unsigned DestLo, DestHi, SrcLo, SrcHi;
59 TRI.splitReg(SrcReg, SrcLo, SrcHi);
65 .addReg(SrcHi, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 566 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
581 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 724 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
739 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | [all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| HexagonFrameLowering.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringX86BaseImpl.h | [all...] |
| IceInstARM32.cpp | [all...] |
| IceTargetLoweringARM32.h | 321 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
[all...] |
| IceTargetLoweringARM32.cpp | [all...] |
