| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 872 unsigned SrcReg1 = getRegForValue(SrcValue1);
873 if (SrcReg1 == 0)
885 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
887 SrcReg1 = ExtReg;
899 .addReg(SrcReg1).addReg(SrcReg2);
902 .addReg(SrcReg1).addImm(Imm);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64SIMDInstrOpt.cpp | 433 unsigned SrcReg1 = MI.getOperand(2).getReg();
453 .addReg(SrcReg1, Src1IsKill)
457 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg1, LaneNumber, &DupDest)) {
460 .addReg(SrcReg1, Src1IsKill)
|
| AArch64InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program_alu.c | 63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
74 fpi->U.I.SrcReg[1] = SrcReg1;
82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
94 fpi->U.I.SrcReg[1] = SrcReg1;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 570 unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
574 SrcsReg1.push_back(SrcReg1);
[all...] |
