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Searched
refs:SubRC
(Results
1 - 20
of
20
) sorted by null
/external/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp
40
const TargetRegisterClass &
SubRC
= *TRI.getRegClass(RCId);
42
if (!RC.hasSubClassEq(&
SubRC
))
47
assert((getSize() >=
SubRC
.getSize() * 8) &&
49
assert(covers(
SubRC
) && "Not all subclasses are covered");
RegisterBankInfo.cpp
141
const TargetRegisterClass *
SubRC
= TRI.getRegClass(SubRCId);
142
for (SuperRegClassIterator SuperRCIt(
SubRC
, &TRI); SuperRCIt.isValid();
152
DEBUG(dbgs() << TRI.getRegClassName(
SubRC
) << ", ");
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp
45
const TargetRegisterClass &
SubRC
= *TRI.getRegClass(RCId);
47
if (!RC.hasSubClassEq(&
SubRC
))
52
assert(getSize() >= TRI.getRegSizeInBits(
SubRC
) &&
54
assert(covers(
SubRC
) && "Not all subclasses are covered");
/external/llvm/lib/CodeGen/
TargetRegisterInfo.cpp
117
const TargetRegisterClass *
SubRC
= getRegClass(It.getID());
118
if (
SubRC
->isAllocatable())
119
return
SubRC
;
/external/swiftshader/third_party/LLVM/utils/TableGen/
CodeGenRegisters.h
157
void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *
SubRC
) {
158
SubClassWithSubReg[SubIdx] =
SubRC
;
CodeGenRegisters.cpp
476
CodeGenRegisterClass *
SubRC
= RegClasses[s];
477
if (!testSubClass(&RC,
SubRC
))
479
//
SubRC
is a sub-class. Grap all its sub-classes so we won't have to
481
RC.SubClasses |=
SubRC
->SubClasses;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
TargetRegisterInfo.cpp
180
const TargetRegisterClass *
SubRC
= getRegClass(It.getID());
181
if (
SubRC
->isAllocatable())
182
return
SubRC
;
/external/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h
143
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *
SubRC
,
SIInstrInfo.h
49
const TargetRegisterClass *
SubRC
) const;
55
const TargetRegisterClass *
SubRC
) const;
SIRegisterInfo.cpp
832
const TargetRegisterClass *
SubRC
,
891
return
SubRC
->getRegister(Index + Channel);
[
all
...]
SIInstrInfo.cpp
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
CodeGenRegisters.cpp
[
all
...]
CodeGenRegisters.h
393
CodeGenRegisterClass *
SubRC
) {
394
SubClassWithSubReg[SubIdx] =
SubRC
;
RISCVCompressInstEmitter.cpp
156
CodeGenRegisterClass
SubRC
= Target.getRegisterClass(DagOpType);
157
return RC.hasSubClass(&
SubRC
);
[
all
...]
/external/llvm/utils/TableGen/
CodeGenRegisters.h
354
CodeGenRegisterClass *
SubRC
) {
355
SubClassWithSubReg[SubIdx] =
SubRC
;
CodeGenRegisters.cpp
861
CodeGenRegisterClass &
SubRC
= *I2;
862
if (RC.SubClasses.test(
SubRC
.EnumValue))
864
if (!testSubClass(&RC, &
SubRC
))
866
//
SubRC
is a sub-class. Grap all its sub-classes so we won't have to
868
RC.SubClasses |=
SubRC
.SubClasses;
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIInstrInfo.h
72
const TargetRegisterClass *
SubRC
) const;
78
const TargetRegisterClass *
SubRC
) const;
[
all
...]
SIInstrInfo.cpp
[
all
...]
/external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp
[
all
...]
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