| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86InterleavedAccess.cpp | 169 Instruction *VecInst, unsigned NumSubVectors, VectorType *SubVecTy,
178 DL.getTypeSizeInBits(SubVecTy) * NumSubVectors &&
185 // Generate N(= NumSubVectors) shuffles of T(= SubVecTy) type.
191 SubVecTy->getVectorNumElements(), 0))));
197 Type *VecBasePtrTy = SubVecTy->getPointerTo(LI->getPointerAddressSpace());
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 668 auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
674 TLI->isLegalInterleavedAccessType(SubVecTy, DL))
675 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL);
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 554 auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
560 TLI->isLegalInterleavedAccessType(SubVecTy, DL))
561 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL);
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 505 Type *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
506 unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy);
|
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 509 Type *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
510 unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy);
|
| ARMISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 665 MVT SubVecTy = tyVector(ty(Ext), ElemTy);
666 SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext),
[all...] |
