| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_inlines.h | 69 case TYPE_U64:
93 case TYPE_U64:
112 case 8: return flt ? TYPE_F64 : (sgn ? TYPE_S64 : TYPE_U64);
139 case TYPE_U64:
151 case TYPE_U64: return TYPE_S64;
|
| nv50_ir_from_tgsi.cpp | 677 return nv50_ir::TYPE_U64;
739 return nv50_ir::TYPE_U64;
[all...] |
| nv50_ir_lowering_nvc0.cpp | 112 bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]);
225 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
254 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
[all...] |
| nv50_ir_build_util.cpp | 378 imm->reg.type = TYPE_U64;
422 return mkOp1v(OP_MOV, TYPE_U64, dst ? dst : getScratch(8), mkImm(u));
568 case TYPE_U64: hTy = TYPE_U32; break;
|
| nv50_ir_print.cpp | 464 case TYPE_U64:
|
| nv50_ir_emit_gm107.cpp | [all...] |
| nv50_ir_emit_nv50.cpp | 591 case TYPE_U64: enc = 0x4; break;
[all...] |
| nv50_ir_lowering_nv50.cpp | 53 case TYPE_S64: fTy = TYPE_U64; break;
60 case TYPE_U64: hTy = TYPE_U32; break;
[all...] |
| nv50_ir.h | 268 TYPE_U64, // 64 bit operations are only lowered after register allocation
[all...] |
| nv50_ir_emit_gk110.cpp | [all...] |
| nv50_ir.cpp | 397 case TYPE_U64:
|
| nv50_ir_emit_nvc0.cpp | [all...] |
| nv50_ir_peephole.cpp | 680 case TYPE_U64:
[all...] |
| /external/ltp/utils/ffsb-6.0-rc2/ |
| parser.h | 30 #define TYPE_U64 0x0002
|
| parser.c | 332 case TYPE_U64:
|
| /external/deqp/external/vulkancts/modules/vulkan/spirv_assembly/ |
| vktSpvAsmTypeTests.cpp | 125 TYPE_U64,
489 return (isSigned) ? TYPE_I64 : TYPE_U64;
[all...] |
