| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 349 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
350 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
380 unsigned TempReg = createResultReg(RC);
381 emitInst(Mips::ADDiu, TempReg)
384 DestReg = TempReg;
610 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
611 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
612 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
616 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
617 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 394 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
395 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
425 unsigned TempReg = createResultReg(RC);
426 emitInst(Mips::ADDiu, TempReg)
429 DestReg = TempReg;
651 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
652 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
653 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
657 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
658 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 752 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
783 &ScratchReg, &TempReg);
787 SingleScratchReg = ScratchReg == TempReg;
850 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
854 .addReg(TempReg, getKillRegState(true))
875 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
[all...] |
| PPCISelDAGToDAG.cpp | 329 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
332 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 762 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
793 &ScratchReg, &TempReg);
797 SingleScratchReg = ScratchReg == TempReg;
860 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
864 .addReg(TempReg, getKillRegState(true))
885 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
[all...] |
| PPCISelDAGToDAG.cpp | 421 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
424 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| GlobalISelEmitter.cpp | [all...] |
