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    Searched refs:UndefReg (Results 1 - 6 of 6) sorted by null

  /external/llvm/lib/Target/AMDGPU/
R600OptimizeVectorRegisters.cpp 67 std::vector<unsigned> UndefReg;
74 UndefReg.push_back(Chan);
159 if (CurrentUndexIdx >= Untouched->UndefReg.size())
162 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
189 std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
230 RSI->UndefReg = UpdatedUndef;
298 unsigned NeededUndefs = 4 - RSI.UndefReg.size();
313 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
R600OptimizeVectorRegisters.cpp 79 std::vector<unsigned> UndefReg;
87 UndefReg.push_back(Chan);
183 if (CurrentUndexIdx >= Untouched->UndefReg.size())
186 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
213 std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
252 RSI->UndefReg = UpdatedUndef;
320 unsigned NeededUndefs = 4 - RSI.UndefReg.size();
335 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
SIISelLowering.cpp     [all...]
  /external/llvm/lib/Target/X86/
X86CallFrameOptimization.cpp 495 unsigned UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
497 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg);
499 .addReg(UndefReg)
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86CallFrameOptimization.cpp 540 unsigned UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
542 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg);
544 .addReg(UndefReg)
  /external/swiftshader/third_party/LLVM/lib/CodeGen/
LiveIntervalAnalysis.cpp 732 unsigned UndefReg = UndefUses[i];
733 (void)getOrCreateInterval(UndefReg);
    [all...]

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