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    Searched refs:UseRC (Results 1 - 8 of 8) sorted by null

  /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
BlackfinISelDAGToDAG.cpp 162 const TargetRegisterClass *UseRC =
164 if (!DefRC || !UseRC)
167 if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) {
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 84 const TargetRegisterClass *UseRC = NULL;
89 UseRC = TLI->getRegClassFor(VT);
119 if (!UseRC)
120 UseRC = RC;
123 TRI->getCommonSubClass(UseRC, RC);
127 UseRC = ComRC;
143 } else if (UseRC) {
144 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
145 DstRC = UseRC;
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 104 const TargetRegisterClass *UseRC = nullptr;
109 UseRC = TLI->getRegClassFor(VT);
139 if (!UseRC)
140 UseRC = RC;
143 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
147 UseRC = ComRC;
163 } else if (UseRC) {
164 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
165 DstRC = UseRC;
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 104 const TargetRegisterClass *UseRC = nullptr;
109 UseRC = TLI->getRegClassFor(VT);
139 if (!UseRC)
140 UseRC = RC;
143 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
147 UseRC = ComRC;
163 } else if (UseRC) {
164 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
166 DstRC = UseRC;
    [all...]
  /external/llvm/lib/Target/AMDGPU/
SIFoldOperands.cpp 210 const TargetRegisterClass *UseRC
223 if (UseRC->getSize() != 8)
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 479 const TargetRegisterClass *UseRC =
487 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
507 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
526 bool IsVSSRC = isVSSRCRegClass(UseRC);
527 bool IsVSFRC = isVSFRCRegClass(UseRC);
537 ResultReg = createResultReg(UseRC);
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 475 const TargetRegisterClass *UseRC =
483 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
505 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
535 ResultReg = createResultReg(UseRC);
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIFoldOperands.cpp 409 const TargetRegisterClass *UseRC
414 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64)
    [all...]

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