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    Searched refs:VGPR (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.h 124 unsigned VGPR;
126 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
127 SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { }
129 bool hasReg() { return VGPR != AMDGPU::NoRegister;}
400 /// \returns VGPR used for \p Dim' work item ID.
SIMachineFunctionInfo.cpp 24 "amdgpu-spill-sgpr-to-vgpr",
222 Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
SIRegisterInfo.cpp 192 // TODO: May need to reserve a VGPR if doing LDS spilling.
446 // VGPRs too. Since we need a VGPR in order to spill SGPRs (this is true
534 Spill.VGPR)
599 .addReg(Spill.VGPR)
632 // VGPR register spill
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.h 195 unsigned VGPR = 0;
199 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
202 bool hasReg() { return VGPR != 0;}
206 // VGPR used for SGPR spills
207 unsigned VGPR;
209 // If the VGPR is a CSR, the stack slot used to save/restore it in the
213 SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {}
217 // SGPR->VGPR spilling support.
220 // Track VGPR + wave index for each subregister of the SGPR spilled to
288 // Add special VGPR input
    [all...]
SIMachineFunctionInfo.cpp 247 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
299 LaneVGPR = SpillVGPRs.back().VGPR;
314 /// \returns VGPR used for \p Dim' work item ID.
SIPeepholeSDWA.cpp     [all...]
SIRegisterInfo.cpp 54 "amdgpu-spill-sgpr-to-vgpr",
204 // TODO: May need to reserve a VGPR if doing LDS spilling.
480 // This differs from buildSpillLoadStore by only scavenging a VGPR. It does not
548 assert((Offset % EltSize) == 0 && "unexpected VGPR spill offset");
565 // VGPRs too. Since we need a VGPR in order to spill SGPRs (this is true
747 // During SGPR spilling to VGPR, determine if the VGPR is defined. The
749 // first spill to this VGPR in the first basic block.
752 VGPRDefined = !SGPRSpillVGPRDefinedSet.insert(Spill.VGPR).second;
754 // Mark the "old value of vgpr" input undef only if this is the first sgp
    [all...]
SIFrameLowering.cpp 598 TII->storeRegToStackSlot(MBB, MBBI, Reg.VGPR, true,
618 TII->loadRegFromStackSlot(MBB, MBBI, Reg.VGPR,
700 assert(Spilled && "failed to spill SGPR to VGPR when allocated");
797 // Since SGPRs are spilled into VGPRs, copy work group ID SGPR to VGPR in
809 // Get work item ID VGPR, and make it live-in again.

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