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    Searched refs:Vec64 (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 164 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
165 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
166 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
168 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
169 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
171 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
172 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
174 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
175 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonISelLowering.h 332 SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
HexagonISelLowering.cpp     [all...]
HexagonISelLoweringHVX.cpp 793 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0});
795 {Vec64, DAG.getTargetConstant(0, dl, MVT::i32)}, DAG);
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 273 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
274 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
275 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
278 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
280 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
281 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
283 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
284 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
    [all...]

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