| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbDxe/ |
| DwUsbDxe.c | 88 WRITE_REG32 (DIEPCTL0, DXEPCTL_USBACTEP | BIT11);
91 WRITE_REG32 (DOEPCTL0, DXEPCTL_USBACTEP);
94 WRITE_REG32 (GOTGINT, ~0);
97 WRITE_REG32 (GINTSTS, ~0);
98 WRITE_REG32 (DIEPINT0, ~0);
99 WRITE_REG32 (DOEPINT0, ~0);
100 WRITE_REG32 (DIEPINT1, ~0);
101 WRITE_REG32 (DOEPINT1, ~0);
104 WRITE_REG32 (DIEPMSK, DXEPMSK_TIMEOUTMSK | DXEPMSK_AHBERMSK | DXEPMSK_XFERCOMPLMSK);
106 WRITE_REG32 (DOEPMSK, DXEPMSK_TIMEOUTMSK | DXEPMSK_AHBERMSK | DXEPMSK_XFERCOMPLMSK);
[all...] |
| DwUsbDxe.h | 22 #define WRITE_REG32(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, Val)
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
| Isp1761UsbDxe.c | 77 WRITE_REG32 (ISP1761_DMA_ENDPOINT_INDEX, ((Endpoint + 2) % ISP1761_NUM_ENDPOINTS));
78 WRITE_REG32 (ISP1761_ENDPOINT_INDEX, Endpoint);
89 WRITE_REG32 (ISP1761_CTRL_FUNCTION, ISP1761_CTRL_FUNCTION_DSEN);
100 WRITE_REG32 (ISP1761_CTRL_FUNCTION, ISP1761_CTRL_FUNCTION_STATUS);
189 WRITE_REG32 (ISP1761_DATA_PORT, DwordBuffer[Index]);
198 WRITE_REG32 (ISP1761_BUFFER_LENGTH, Size);
201 WRITE_REG32 (ISP1761_DATA_PORT, DwordBuffer[0]);
207 WRITE_REG32 (ISP1761_DATA_PORT, DwordBuffer[0]);
297 WRITE_REG32 (ISP1761_ADDRESS, Request->Value | ISP1761_ADDRESS_DEVEN);
333 WRITE_REG32 (ISP1761_ENDPOINT_MAX_PACKET_SIZE, EPDesc->MaxPacketSize);
[all...] |
| Isp1761UsbDxe.h | 22 #define WRITE_REG32(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, Val)
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/SasV1Dxe/ |
| SasV1Dxe.c | 36 #define WRITE_REG32(Base, Offset, Val) MmioWrite32 ((Base) + (Offset), (Val))
424 WRITE_REG32(base, DLVRY_Q_0_WR_PTR + queue * 0x14, ++w % QUEUE_SLOTS);
449 WRITE_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue), w);
451 WRITE_REG32(base, OQ_INT_SRC, BIT(queue));
518 WRITE_REG32(base, DLVRY_QUEUE_ENABLE, 0xffffffff);
519 WRITE_REG32(base, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
520 WRITE_REG32(base, DEVICE_MSG_WORK_MODE, 0x1);
521 WRITE_REG32(base, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
522 WRITE_REG32(base, HGC_ERR_STAT_EN, 0x401);
523 WRITE_REG32(base, CFG_1US_TIMER_TRSH, 0x64);
[all...] |
