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  /external/libxaac/decoder/armv8/
ixheaacd_shiftrountine_with_round.s 6 stp X20, X21, [sp, #-16]!
17 ldp X20, X21, [sp], #16
ixheaacd_shiftrountine_with_round_eld.s 6 stp X20, X21, [sp, #-16]!
17 ldp X20, X21, [sp], #16
ixheaacd_cos_sin_mod_loop2.s 12 stp X20, X21, [sp, #-16]!
18 ldp X20, X21, [sp], #16
ixheaacd_cos_sin_mod_loop1.s 12 stp X20, X21, [sp, #-16]!
18 ldp X20, X21, [sp], #16
ixheaacd_fft32x32_ld2_armv8.s 8 stp X20, X21, [sp, #-16]!
16 ldp X20, X21, [sp], #16
ixheaacd_pre_twiddle.s 32 stp X20, X21, [sp, #-16]!
35 ldp X20, X21, [sp], #16
  /art/runtime/arch/arm64/
registers_arm64.h 48 X21 = 21,
callee_save_frame_arm64.h 39 (1 << art::arm64::X20) | (1 << art::arm64::X21) | (1 << art::arm64::X22) |
  /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
PPCBaseInfo.h 52 case R21: case X21: case F21: case V21: case CR5GT: return 21;
  /external/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.h 53 case AArch64::X21: return AArch64::W21;
93 case AArch64::W21: return AArch64::X21;
  /art/compiler/jni/quick/arm64/
calling_convention_arm64.cc 65 Arm64ManagedRegister::FromXRegister(X21),
  /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
PPCFrameLowering.h 262 {PPC::X21, -88},
PPCRegisterInfo.cpp 162 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
188 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.h 53 case AArch64::X21: return AArch64::W21;
93 case AArch64::W21: return AArch64::X21;
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/Disassembler/
RISCVDisassembler.cpp 64 RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
  /art/compiler/utils/arm64/
managed_register_arm64_test.cc 502 reg_o = Arm64ManagedRegister::FromXRegister(X21);
504 EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromXRegister(X21)));
510 EXPECT_EQ(X21, reg.AsOverlappingXRegister());
616 EXPECT_TRUE(vixl::aarch64::x21.Is(Arm64Assembler::reg_x(X21)));
    [all...]
  /device/linaro/bootloader/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/
DefaultExceptionHandler.c 82 case 0x21: AbortCause = "Alignment fault"; break;
111 case 0x21: DescribeInstructionOrDataAbort ("Instruction abort", Iss); return;
225 DEBUG ((EFI_D_ERROR, " X20 0x%016lx X21 0x%016lx X22 0x%016lx X23 0x%016lx\n", SystemContext.SystemContextAArch64->X20, SystemContext.SystemContextAArch64->X21, SystemContext.SystemContextAArch64->X22, SystemContext.SystemContextAArch64->X23));
  /external/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AsmBackend.cpp 460 // X21/X22 pair = 0x00000002,
470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
  /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
AArch64GenCallingConv.inc 111 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
355 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
708 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
812 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
    [all...]
AArch64GenRegisterInfo.inc 257 X21 = 237,
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/
PPCDisassembler.cpp 202 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
213 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
  /device/linaro/bootloader/edk2/MdePkg/Include/Protocol/
DebugSupport.h 559 UINT64 X21;
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AsmBackend.cpp 517 // X21/X22 pair = 0x00000002,
527 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
  /external/guava/guava-tests/benchmark/com/google/common/base/
EnumsBenchmark.java 80 X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32, X33, X34, X35, X36, X37,
89 X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32, X33, X34, X35, X36, X37, X38, X39,
  /external/llvm/lib/Target/PowerPC/Disassembler/
PPCDisassembler.cpp 191 PPC::X20, PPC::X21, PPC::X22, PPC::X23,

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