| /external/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 377 addhn2 v0.16b, v1.8h, v2.8h
378 addhn2 v0.8h, v1.4s, v2.4s
379 addhn2 v0.4s, v1.2d, v2.2d
381 // CHECK: addhn2 v0.16b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x4e]
382 // CHECK: addhn2 v0.8h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x4e]
383 // CHECK: addhn2 v0.4s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x4e]
|
| arm64-advsimd.s | 40 addhn2.16b v0, v0, v0
42 addhn2.8h v0, v0, v0
44 addhn2.4s v0, v0, v0
47 ; CHECK: addhn2.16b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x4e]
49 ; CHECK: addhn2.8h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x4e]
51 ; CHECK: addhn2.4s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x4e]
[all...] |
| neon-diagnostics.s | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 377 addhn2 v0.16b, v1.8h, v2.8h
378 addhn2 v0.8h, v1.4s, v2.4s
379 addhn2 v0.4s, v1.2d, v2.2d
381 // CHECK: addhn2 v0.16b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x4e]
382 // CHECK: addhn2 v0.8h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x4e]
383 // CHECK: addhn2 v0.4s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x4e]
|
| arm64-advsimd.s | 40 addhn2.16b v0, v0, v0
42 addhn2.8h v0, v0, v0
44 addhn2.4s v0, v0, v0
47 ; CHECK: addhn2.16b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x4e]
49 ; CHECK: addhn2.8h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x4e]
51 ; CHECK: addhn2.4s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x4e]
[all...] |
| neon-diagnostics.s | [all...] |
| /external/capstone/suite/MC/AArch64/ |
| neon-3vdiff.s.cs | 129 0x20,0x40,0x22,0x4e = addhn2 v0.16b, v1.8h, v2.8h
130 0x20,0x40,0x62,0x4e = addhn2 v0.8h, v1.4s, v2.4s
131 0x20,0x40,0xa2,0x4e = addhn2 v0.4s, v1.2d, v2.2d
|
| /external/v8/src/arm64/ |
| macro-assembler-arm64.h | 384 V(addhn2, Addhn2) \
[all...] |
| assembler-arm64.h | [all...] |
| simulator-arm64.h | [all...] |
| assembler-arm64.cc | [all...] |
| simulator-arm64.cc | [all...] |
| simulator-logic-arm64.cc | 2764 LogicVRegister Simulator::addhn2(VectorFormat vform, LogicVRegister dst, function in class:v8::internal::Simulator
[all...] |
| /external/vixl/test/aarch64/ |
| test-trace-aarch64.cc | 632 __ addhn2(v16.V16B(), v21.V8H(), v20.V8H());
633 __ addhn2(v0.V4S(), v2.V2D(), v17.V2D());
634 __ addhn2(v31.V8H(), v7.V4S(), v17.V4S());
[all...] |
| test-cpu-features-aarch64.cc | 741 TEST_NEON(addhn2_0, addhn2(v0.V16B(), v1.V8H(), v2.V8H()))
742 TEST_NEON(addhn2_1, addhn2(v0.V8H(), v1.V4S(), v2.V4S()))
743 TEST_NEON(addhn2_2, addhn2(v0.V4S(), v1.V2D(), v2.V2D()))
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| macro-assembler-aarch64.h | [all...] |
| simulator-aarch64.h | [all...] |
| logic-aarch64.cc | 3486 LogicVRegister Simulator::addhn2(VectorFormat vform, function in class:vixl::aarch64::Simulator
[all...] |
| simulator-aarch64.cc | [all...] |
| assembler-aarch64.cc | [all...] |
