| /external/u-boot/drivers/pinctrl/mvebu/ |
| pinctrl-mvebu.h | 16 * @base_reg: controller base address for this bank
23 void *base_reg; member in struct:mvebu_pinctrl_priv
|
| pinctrl-mvebu.c | 48 clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,
55 clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,
113 clrsetbits_le32(priv->base_reg + reg_offset,
174 clrsetbits_le32(priv->base_reg + reg_offset,
194 priv->base_reg = devfdt_get_addr_ptr(dev);
195 if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
|
| /external/u-boot/drivers/pinctrl/broadcom/ |
| pinctrl-bcm283x.c | 26 u32 *base_reg; member in struct:bcm283x_pinctrl_priv
41 clrsetbits_le32(&priv->base_reg[reg_offset],
51 val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]);
117 priv->base_reg = dev_read_addr_ptr(dev);
118 if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
|
| /external/u-boot/arch/arm/mach-tegra/ |
| clock.c | 590 u32 base_reg, misc_reg; local
596 base_reg = readl(&pll->pll_base);
599 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
600 base_reg |= m << pllinfo->m_shift;
602 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
603 base_reg |= n << pllinfo->n_shift;
605 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
606 base_reg |= p << pllinfo->p_shift;
613 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
614 base_reg |= PLL_ENABLE_MASK
[all...] |
| /art/dex2oat/linker/arm/ |
| relative_patcher_thumb2_test.cc | 278 static uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg,
281 return arm::CodeGeneratorARMVIXL::EncodeBakerReadBarrierFieldData(base_reg, holder_reg, narrow);
284 static uint32_t EncodeBakerReadBarrierArrayData(uint32_t base_reg) {
285 return arm::CodeGeneratorARMVIXL::EncodeBakerReadBarrierArrayData(base_reg);
292 std::vector<uint8_t> CompileBakerOffsetThunk(uint32_t base_reg,
296 /* literal_offset */ 0u, EncodeBakerReadBarrierFieldData(base_reg, holder_reg, narrow));
300 std::vector<uint8_t> CompileBakerArrayThunk(uint32_t base_reg) {
302 /* literal_offset */ 0u, EncodeBakerReadBarrierArrayData(base_reg));
680 for (uint32_t base_reg : kBakerValidRegs) {
682 uint32_t ldr = kLdrWInsn | offset | (base_reg << 16) | (ref_reg << 12)
[all...] |
| /art/dex2oat/linker/arm64/ |
| relative_patcher_arm64_test.cc | 519 static uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg, uint32_t holder_reg) {
520 return arm64::CodeGeneratorARM64::EncodeBakerReadBarrierFieldData(base_reg, holder_reg);
523 static uint32_t EncodeBakerReadBarrierArrayData(uint32_t base_reg) {
524 return arm64::CodeGeneratorARM64::EncodeBakerReadBarrierArrayData(base_reg);
531 std::vector<uint8_t> CompileBakerOffsetThunk(uint32_t base_reg, uint32_t holder_reg) {
533 /* literal_offset */ 0u, EncodeBakerReadBarrierFieldData(base_reg, holder_reg));
537 std::vector<uint8_t> CompileBakerArrayThunk(uint32_t base_reg) {
539 /* literal_offset */ 0u, EncodeBakerReadBarrierArrayData(base_reg));
[all...] |
| /external/mesa3d/src/util/ |
| register_allocate.h | 57 unsigned int base_reg, unsigned int reg);
|
| register_allocate.c | 261 * Adds a conflict between base_reg and reg, and also between reg and
262 * anything that base_reg conflicts with.
270 unsigned int base_reg, unsigned int reg)
274 ra_add_reg_conflict(regs, reg, base_reg);
276 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
277 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
|
| /external/v8/src/x64/ |
| code-stubs-x64.cc | 273 Register base_reg = r15; local
274 __ Move(base_reg, next_address);
275 __ movp(prev_next_address_reg, Operand(base_reg, kNextOffset));
276 __ movp(prev_limit_reg, Operand(base_reg, kLimitOffset));
277 __ addl(Operand(base_reg, kLevelOffset), Immediate(1));
323 __ subl(Operand(base_reg, kLevelOffset), Immediate(1));
324 __ movp(Operand(base_reg, kNextOffset), prev_next_address_reg);
325 __ cmpp(prev_limit_reg, Operand(base_reg, kLimitOffset));
390 __ movp(Operand(base_reg, kLimitOffset), prev_limit_reg);
|
| macro-assembler-x64.h | 71 StackArgumentsAccessor(Register base_reg, int argument_count_immediate,
75 : base_reg_(base_reg),
82 StackArgumentsAccessor(Register base_reg, Register argument_count_reg,
86 : base_reg_(base_reg),
93 StackArgumentsAccessor(Register base_reg,
[all...] |
| disasm-x64.cc | 340 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Scripts/Ds5/ |
| cmd_load_symbols.py | 40 base_reg = re.compile("(.*)")
variable
|
| /art/compiler/optimizing/ |
| code_generator_arm64.h | [all...] |
| code_generator_arm_vixl.h | 563 // MOVW+MOVT to load the offset to base_reg and then ADD base_reg, PC. The offset
[all...] |
| code_generator_arm64.cc | 963 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
980 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
[all...] |
| code_generator_mips.cc | 3032 Register base_reg = index.IsConstant() ? obj : TMP; local
7979 Register base_reg = (invoke->HasPcRelativeMethodLoadKind() && !is_r6 && !has_irreducible_loops) local
[all...] |
| code_generator_mips64.cc | [all...] |
| code_generator_arm_vixl.cc | 1971 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
1978 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
1988 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
[all...] |
| /external/mesa3d/src/intel/compiler/ |
| brw_vec4_reg_allocate.cpp | 138 for (int base_reg = j;
139 base_reg < j + class_sizes[i];
140 base_reg++) {
141 ra_add_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg);
|
| brw_fs_reg_allocate.cpp | 217 for (int base_reg = j;
218 base_reg < j + (class_sizes[i] + 1) / 2;
219 base_reg++) {
220 ra_add_reg_conflict(regs, base_reg, reg);
231 for (int base_reg = j;
232 base_reg < j + class_sizes[i];
233 base_reg++) {
234 ra_add_reg_conflict(regs, base_reg, reg);
[all...] |
| /external/mesa3d/src/amd/vulkan/ |
| radv_cmd_buffer.c | 582 uint32_t base_reg = pipeline->user_data_0[stage]; local
587 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
610 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT]; local
633 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
875 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL]; local
878 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
888 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL]; local
892 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
898 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX]; local
902 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4
1669 uint32_t base_reg = pipeline->user_data_0[stage]; local
3167 uint32_t base_reg = pipeline->user_data_0[stage]; local
3174 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0; local
3214 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 426 uint32_t base_reg; local
439 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
440 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
442 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
448 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | [all...] |
| /external/v8/src/interpreter/ |
| interpreter-assembler.cc | 276 Node* base_reg = RegisterLocation( local
279 return RegListNodePair(base_reg, reg_count);
[all...] |
| /external/pcre/dist2/src/ |
| pcre2_jit_compile.c | 2131 int from_sp, base_reg, offset, i; local
[all...] |
