| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_compute.c | 44 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
45 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
46 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
63 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
74 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
85 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
|
| brw_draw.c | 209 brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT,
231 brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
233 brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
236 brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
239 brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
241 brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
244 brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
[all...] |
| brw_pipe_control.c | 519 brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE,
|
| hsw_sol.c | 94 brw_load_register_mem(brw, HSW_CS_GPR(0), obj->prim_count_bo,
|
| brw_context.h | [all...] |
| intel_batchbuffer.c | 1225 brw_load_register_mem(struct brw_context *brw, function
[all...] |
