| /external/u-boot/drivers/net/fsl-mc/dpio/ |
| qbman_portal.h | 111 /* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
126 /* decode a field from a cacheline */
128 const uint32_t *cacheline)
130 return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
134 /* encode a field to a cacheline */
136 uint32_t *cacheline, uint32_t val)
138 cacheline[code->word] =
139 r32_uint32_t(code->lsoffset, code->width, cacheline[code->word])
144 uint64_t *cacheline, uint64_t val)
146 cacheline[code->word / 2] = val
[all...] |
| /external/virglrenderer/src/gallium/auxiliary/util/ |
| u_cpu_detect.h | 53 unsigned cacheline; member in struct:util_cpu_caps
|
| u_cpu_detect.c | 335 /* Make the fallback cacheline size nonzero so that it can be
338 util_cpu_caps.cacheline = sizeof(void *);
345 util_cpu_caps.cacheline = 32;
351 unsigned int cacheline; local
381 cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
382 if (cacheline > 0)
383 util_cpu_caps.cacheline = cacheline;
413 util_cpu_caps.cacheline = regs2[2] & 0xFF;
434 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline)
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_cpu_detect.h | 53 unsigned cacheline; member in struct:util_cpu_caps
|
| u_cpu_detect.c | 395 /* Make the fallback cacheline size nonzero so that it can be
398 util_cpu_caps.cacheline = sizeof(void *);
405 util_cpu_caps.cacheline = 32;
411 unsigned int cacheline; local
442 cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
443 if (cacheline > 0)
444 util_cpu_caps.cacheline = cacheline;
491 unsigned int cacheline; local
493 cacheline = regs2[2] & 0xFF
[all...] |
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_texture.c | 82 * resources. Otherwise we'd want the max of cacheline size and 16 (max size
86 unsigned mip_align = MAX2(64, util_cpu_caps.cacheline);
124 lpr->row_stride[level] = align(nblocksx * block_size, util_cpu_caps.cacheline);
|
| /external/u-boot/include/configs/ |
| T4240QDS.h | 507 * interleaving. It can be cacheline, page, bank, superbank.
513 #define CTRL_INTLV_PREFERED cacheline
|
| T208xQDS.h | 212 #define CTRL_INTLV_PREFERED cacheline
|
| T208xRDB.h | 196 #define CTRL_INTLV_PREFERED cacheline
|
| T4240RDB.h | 655 * interleaving. It can be cacheline, page, bank, superbank.
661 #define CTRL_INTLV_PREFERED cacheline
|
