| /external/mesa3d/src/gallium/drivers/nouveau/ |
| nouveau_vp3_video.h | 171 uint32_t *cbcr, uint32_t *cbcr2)
175 *cbcr = *y2 * 2;
176 *cbcr2 = *cbcr + w * (nouveau_vp3_video_align(dec->base.height)>>6);
181 size = (2 * (*cbcr2 - *cbcr) + *cbcr) << 8;
184 dec->ref_stride, size, *y2<<8, *cbcr<<8, *cbcr2<<8);
185 *y2 = *cbcr = *cbcr2 = 0;
|
| /external/u-boot/arch/arm/mach-snapdragon/ |
| clock-snapdragon.c | 18 /* CBCR register fields */
25 void clk_enable_cbc(phys_addr_t cbcr)
27 setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
29 while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
|
| clock-snapdragon.h | 40 void clk_enable_cbc(phys_addr_t cbcr);
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv98_video_ppp.c | 34 uint32_t y2, cbcr, cbcr2, i; local
51 nouveau_vp3_ycbcr_offsets(dec, &y2, &cbcr, &cbcr2);
63 PUSH_DATA (push, in_addr + cbcr); // 710
|
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_video_ppp.c | 34 uint32_t y2, cbcr, cbcr2, i; local
51 nouveau_vp3_ycbcr_offsets(dec, &y2, &cbcr, &cbcr2);
63 PUSH_DATA (push, in_addr + cbcr); // 710
|
| /external/u-boot/arch/arc/lib/ |
| cache.c | 252 union bcr_clust_cfg cbcr; local
254 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
255 return cbcr.fields.c;
|
| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| mmc.h | 34 u32 cbcr; /* 0x48 CIU byte count */ member in struct:sunxi_mmc
|
| /external/ImageMagick/MagickCore/ |
| quantum-export.c | 1353 cbcr[4]; local
[all...] |
| quantum-import.c | 1408 cbcr[4]; local
[all...] |
| /external/pdfium/core/fxcodec/codec/ |
| fx_codec_jpx_opj.cpp | 173 bool sycc420_must_extend_cbcr(OPJ_UINT32 y, OPJ_UINT32 cbcr) {
174 return (y & 1) && (cbcr == y / 2);
|
