/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ia32/ |
ReadCr0.c | 24 mov eax, cr0
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WriteCr0.c | 25 mov cr0, eax
local
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DisablePaging32.c | 36 mov eax, cr0
39 mov cr0, eax
local
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EnablePaging32.c | 36 mov eax, cr0
39 mov cr0, eax
local
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DisablePaging32.S | 45 movl %cr0, %eax
48 movl %eax, %cr0
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/device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ia32/ |
ReadCr0.c | 19 Reads the current value of the Control Register 0 (CR0).
21 Reads and returns the current value of CR0. This function is only available
25 @return The value of the Control Register 0 (CR0).
35 mov eax, cr0
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DisableCache.c | 16 Set CD bit and clear NW bit of CR0 followed by a WBINVD.
18 Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
29 mov eax, cr0
32 mov cr0, eax
local
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EnableCache.c | 16 Perform a WBINVD and clear both the CD and NW bits of CR0.
19 bits of CR0 to 0. This function is only available on IA-32 and x64.
30 mov eax, cr0
33 mov cr0, eax
local
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WriteCr0.c | 16 Writes a value to Control Register 0 (CR0).
18 Writes and returns a new value to CR0. This function is only available on
21 @param Value The value to write to CR0.
23 @return The value written to CR0.
34 mov cr0, eax
local
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DisablePaging32.c | 32 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
66 mov eax, cr0
69 mov cr0, eax
local
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EnablePaging32.c | 20 Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
34 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
69 mov eax, cr0
72 mov cr0, eax
local
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DisableCache.S | 18 # Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
34 movl %cr0, %eax
37 movl %eax, %cr0
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EnableCache.S | 18 # Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
19 # the NW bit of CR0 to 0
35 movl %cr0, %eax
38 movl %eax, %cr0
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/external/slf4j/slf4j-migrator/src/main/java/org/slf4j/migrator/line/ |
JCLRuleSet.java | 43 SingleConversionRule cr0 = new SingleConversionRule(Pattern.compile("import\\s*+org.apache.commons.logging.LogFactory;"), local 58 conversionRuleList.add(cr0);
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/external/u-boot/arch/x86/cpu/ |
call32.S | 43 movl %cr0, %eax 45 movl %eax, %cr0
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start16.S | 33 movl %cr0, %eax 35 movl %eax, %cr0 43 movl %cr0, %eax 45 movl %eax, %cr0
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wakeup.S | 49 movl %cr0, %eax 51 movl %eax, %cr0
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/external/u-boot/include/faraday/ |
ftpmu010.h | 142 #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) 143 #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) 147 #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) 148 #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) 172 void ftpmu010_sdram_clk_disable(unsigned int cr0);
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/external/syzkaller/executor/ |
kvm.S | 13 mov %cr0, %eax 15 mov %eax, %cr0 26 mov %cr0, %eax 28 mov %eax, %cr0 44 mov %cr0, %eax 46 mov %eax, %cr0 56 mov %cr0, %eax 58 mov %eax, %cr0 68 mov %cr0, %eax 70 mov %eax, %cr0 [all...] |
/device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/X64/ |
DisableCache.S | 18 # Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
34 movq %cr0, %rax
37 movq %rax, %cr0
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EnableCache.S | 18 # Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
19 # the NW bit of CR0 to 0
35 movq %cr0, %rax
38 movq %rax, %cr0
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/external/u-boot/arch/x86/cpu/intel_common/ |
car.S | 101 /* Enable cache (CR0.CD = 0, CR0.NW = 0) */ 102 movl %cr0, %eax 105 movl %eax, %cr0 129 movl %cr0, %eax 131 movl %eax, %cr0 161 movl %cr0, %eax 163 movl %eax, %cr0 179 movl %cr0, %eax 181 movl %eax, %cr0 [all...] |
/external/u-boot/drivers/power/ |
ftpmu010.c | 68 void ftpmu010_sdram_clk_disable(unsigned int cr0) 74 pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
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/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/IA32/ |
CpuIA32.c | 104 mov eax, cr0
109 mov eax, cr0
111 mov cr0, eax
local 122 mov eax, cr0
124 mov cr0, eax
local
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/ |
CpuIA32.c | 116 mov eax, cr0
121 mov eax, cr0
123 mov cr0, eax
134 mov eax, cr0
136 mov cr0, eax
114 mov cr0, eax local 127 mov cr0, eax local
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