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  /external/u-boot/drivers/ddr/marvell/axp/
ddr3_hw_training.c 1020 u32 *max, u32 *cs_max)
1038 *cs_max = cs;
1088 u32 min, max, cs_max; local
1096 &max_read_sample_delay, &cs_max);
1102 ddr3_get_min_max_rl_phase(dram_info, &min, &max, cs_max);
ddr3_hw_training.h 383 u32 *max, u32 *cs_max);

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