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Searched
refs:davinci_eth_phy_write
(Results
1 - 5
of
5
) sorted by null
/external/u-boot/arch/arm/mach-davinci/
dp83848.c
75
davinci_eth_phy_write
(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
92
davinci_eth_phy_write
(phy_addr, DP83848_CTL_REG, tmp);
100
davinci_eth_phy_write
(phy_addr, DP83848_ANA_REG, tmp);
108
davinci_eth_phy_write
(phy_addr, DP83848_CTL_REG, tmp);
112
davinci_eth_phy_write
(phy_addr, DP83848_CTL_REG, tmp);
et1011c.c
32
davinci_eth_phy_write
(phy_addr, MII_PHY_CONFIG_REG,
lxt972.c
53
davinci_eth_phy_write
(phy_addr, PHY_LXT971_DIG_CFG, tmp);
82
davinci_eth_phy_write
(phy_addr, PHY_LXT971_INT_ENABLE, 0);
97
davinci_eth_phy_write
(phy_addr, MII_BMCR, tmp);
/external/u-boot/drivers/net/
davinci_emac.c
232
int
davinci_eth_phy_write
(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
function
331
davinci_eth_phy_write
(phy_addr, MII_BMCR, val);
338
davinci_eth_phy_write
(phy_addr, MII_ADVERTISE, val);
347
davinci_eth_phy_write
(phy_addr, MII_CTRL1000, val);
353
davinci_eth_phy_write
(phy_addr, MII_BMCR, tmp);
391
return
davinci_eth_phy_write
(addr, reg, value) ? 0 : 1;
887
davinci_eth_phy_write
(active_phy_addr[i], PHY_CONF_REG, tmp);
davinci_emac.h
294
int
davinci_eth_phy_write
(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
Completed in 430 milliseconds