/external/u-boot/drivers/ddr/marvell/axp/ |
ddr3_pbs.c | 201 ddr3_write_pup_reg( 641 ddr3_write_pup_reg( 653 ddr3_write_pup_reg(PUP_PBS_RX + 700 ddr3_write_pup_reg 712 ddr3_write_pup_reg 748 ddr3_write_pup_reg(PUP_DQS_RD, CS0, 886 ddr3_write_pup_reg(PUP_DQS_RD, CS0, PUP_BC, 0, INIT_RL_DELAY); 958 ddr3_write_pup_reg(PUP_DQS_RD, CS0, pup + ecc * ECC_PUP, 0, 983 ddr3_write_pup_reg(PUP_DQS_RD, CS0, pup + ecc * ECC_PUP, 1010 ddr3_write_pup_reg(PUP_PBS_RX + DQS_DQ_NUM, CS0 [all...] |
ddr3_dqs.c | 397 ddr3_write_pup_reg(adll_addr, cs, pup + 986 ddr3_write_pup_reg(PUP_DQS_RD, cs, 1087 ddr3_write_pup_reg(PUP_DQS_RD, [all...] |
ddr3_write_leveling.c | 357 ddr3_write_pup_reg 388 ddr3_write_pup_reg 551 ddr3_write_pup_reg(PUP_WL_MODE, 626 ddr3_write_pup_reg(PUP_WL_MODE, cs, [all...] |
ddr3_hw_training.h | 326 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
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ddr3_read_leveling.c | 292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, 442 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); 796 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); [all...] |
ddr3_sdram.c | 415 ddr3_write_pup_reg(pup_addr +
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ddr3_hw_training.c | 547 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) function
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