| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| clock.h | 53 * @param divm input divider
61 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
80 * @param divm returns input divider
88 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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| warmboot.h | 71 u32 divm:5; member in struct:pllx_base_reg::__anon46750
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| /external/u-boot/arch/arm/mach-tegra/ |
| clock.c | 89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
113 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
535 u32 base, divm; local
552 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
566 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
567 do_div(rate, divm);
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| cpu.c | 170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
187 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
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| /external/u-boot/arch/arm/mach-tegra/tegra20/ |
| warmboot.c | 153 u32 divm, divn, divp, cpcon, lfcon; local
155 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
158 scratch2.pllm_base_divm = divm;
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| /external/u-boot/drivers/clk/ |
| clk_stm32h7.c | 320 u8 divm; member in struct:pll_psc
333 .divm = 4,
394 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;
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| clk_stm32mp1.c | 814 int divm, divn, divy, src; local
834 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
838 debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
850 * / (DIVM + 1) * (DIVy + 1)
852 * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
859 ((unsigned long long)(divm + 1) *
862 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
[all...] |
| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| clock.c | 1066 u32 divm, divn, divp, cpcon; local
1086 for (divm = 1; divm < max_m && best_diff; divm++) {
1087 cf = ref / divm;
1107 best_m = divm;
[all...] |
