| /external/elfutils/lib/ |
| next_prime.c | 38 size_t divn = 3; local
39 size_t sq = divn * divn;
41 while (sq < candidate && candidate % divn != 0)
44 ++divn;
45 sq += 4 * divn;
48 ++divn;
51 return candidate % divn != 0;
|
| /external/u-boot/arch/arm/mach-uniphier/clk/ |
| pll.h | 15 unsigned int ssc_rate, unsigned int divn);
|
| pll-base-ld20.c | 32 unsigned int ssc_rate, unsigned int divn)
46 divn * 512));
53 divn * 512));
|
| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| clock.h | 54 * @param divn feedback divider
61 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
81 * @param divn returns feedback divider
88 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
364 * @param n PLL feedback divider(DIVN)
365 * @param m PLL input divider(DIVN)
|
| warmboot.h | 73 u32 divn:10; member in struct:pllx_base_reg::__anon46750
|
| /external/u-boot/arch/arm/mach-tegra/ |
| cpu.c | 170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
188 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
202 if (divn > 600)
|
| clock.c | 89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
103 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
113 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
581 * @param n PLL feedback divider(DIVN)
582 * @param m PLL input divider(DIVN)
|
| /external/u-boot/arch/arm/mach-tegra/tegra20/ |
| warmboot.c | 153 u32 divm, divn, divp, cpcon, lfcon; local
155 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
159 scratch2.pllm_base_divn = divn;
|
| warmboot_avp.c | 168 pllx_base.divn = scratch3.pllx_base_divn;
|
| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| clock.c | 1066 u32 divm, divn, divp, cpcon; local
1093 divn = vco / cf;
1094 if (divn >= max_n)
1097 diff = vco - divn * cf;
1098 if (divn + 1 < max_n && diff > cf / 2) {
1099 divn++;
1108 best_n = divn;
[all...] |
| /external/u-boot/drivers/clk/ |
| clk_stm32h7.c | 321 u16 divn; member in struct:pll_psc
334 .divn = 80,
400 pll1divr |= (sys_pll_psc.divn - 1);
|
| clk_stm32mp1.c | 814 int divm, divn, divy, src; local
835 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
838 debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
849 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
852 * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
858 (((divn + 1) << 13) + fracv),
862 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
[all...] |
