| /external/llvm/test/MC/PowerPC/ |
| ppc64-encoding.s | 430 # CHECK-BE: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96]
431 # CHECK-LE: divwu 2, 3, 4 # encoding: [0x96,0x23,0x43,0x7c]
432 divwu 2, 3, 4
433 # CHECK-BE: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97]
434 # CHECK-LE: divwu. 2, 3, 4 # encoding: [0x97,0x23,0x43,0x7c]
435 divwu. 2, 3, 4
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| ppc64-encoding.s | 503 # CHECK-BE: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96]
504 # CHECK-LE: divwu 2, 3, 4 # encoding: [0x96,0x23,0x43,0x7c]
505 divwu 2, 3, 4
506 # CHECK-BE: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97]
507 # CHECK-LE: divwu. 2, 3, 4 # encoding: [0x97,0x23,0x43,0x7c]
508 divwu. 2, 3, 4
[all...] |
| /external/v8/src/ppc/ |
| disasm-ppc.cc | 774 case DIVWU: {
775 Format(instr, "divwu'o'. 'rt, 'ra, 'rb");
[all...] |
| assembler-ppc.h | [all...] |
| assembler-ppc.cc | 910 void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o, function in class:v8::internal::Assembler
912 xo_form(EXT2 | DIVWU, dst, src1, src2, o, r);
[all...] |
| constants-ppc.h | [all...] |
| /external/v8/src/compiler/ppc/ |
| code-generator-ppc.cc | [all...] |
