| /external/u-boot/arch/nds32/lib/ |
| asm-offsets.c | 65 OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
66 OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
67 OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
68 OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
69 OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
70 OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
71 OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
72 OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
73 OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
74 OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 *
[all...] |
| /external/u-boot/arch/arm/mach-sunxi/ |
| dram_sun4i.c | 137 clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
139 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
142 clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
145 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
171 clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
173 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
180 clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
185 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
|
| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| dram_sun4i.h | 45 u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ member in struct:sunxi_dram_reg
|
| /external/u-boot/include/synopsys/ |
| dwcddr21mctl.h | 24 unsigned int dllcr[10]; /* DLL Control */ member in struct:dwcddr21mctl
|
