| /external/libdrm/etnaviv/ |
| etnaviv_pipe.c | 49 ret = drmCommandWrite(dev->fd, DRM_ETNAVIV_WAIT_FENCE, &req, sizeof(req));
|
| etnaviv_bo.c | 336 return drmCommandWrite(bo->dev->fd, DRM_ETNAVIV_GEM_CPU_PREP,
346 drmCommandWrite(bo->dev->fd, DRM_ETNAVIV_GEM_CPU_FINI,
|
| /external/libdrm/amdgpu/ |
| amdgpu_gpu_info.c | 43 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
58 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
77 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
92 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
109 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
129 r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
330 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
|
| /external/libdrm/freedreno/msm/ |
| msm_bo.c | 76 return drmCommandWrite(bo->dev->fd, DRM_MSM_GEM_CPU_PREP, &req, sizeof(req));
85 drmCommandWrite(bo->dev->fd, DRM_MSM_GEM_CPU_FINI, &req, sizeof(req));
|
| msm_pipe.c | 90 ret = drmCommandWrite(dev->fd, DRM_MSM_WAIT_FENCE, &req, sizeof(req));
133 drmCommandWrite(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_CLOSE,
|
| /external/libdrm/nouveau/ |
| abi16.c | 137 ret = drmCommandWrite(drm->fd, DRM_NOUVEAU_GROBJ_ALLOC,
224 drmCommandWrite(drm->fd, DRM_NOUVEAU_CHANNEL_FREE,
230 drmCommandWrite(drm->fd, DRM_NOUVEAU_GPUOBJ_FREE,
|
| nouveau.c | 532 return drmCommandWrite(drm->fd, DRM_NOUVEAU_SETPARAM, &r, sizeof(r));
852 ret = drmCommandWrite(drm->fd, DRM_NOUVEAU_GEM_CPU_PREP,
|
| /external/libdrm/omap/ |
| omap_drm.c | 156 return drmCommandWrite(dev->fd, DRM_OMAP_SET_PARAM, &req, sizeof(req));
461 return drmCommandWrite(bo->dev->fd,
472 return drmCommandWrite(bo->dev->fd,
|
| /external/mesa3d/src/gallium/winsys/svga/drm/ |
| vmw_screen_ioctl.c | 127 (void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_CONTEXT,
410 (void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_SURFACE,
470 * the flags field. The structure size sent to drmCommandWrite must match
476 ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_EXECBUF, &arg, argsize);
573 drmCommandWrite(region->drm_fd, DRM_VMW_UNREF_DMABUF, &arg, sizeof(arg));
651 return drmCommandWrite(region->drm_fd, DRM_VMW_SYNCCPU, &arg, sizeof(arg));
677 (void) drmCommandWrite(region->drm_fd, DRM_VMW_SYNCCPU, &arg, sizeof(arg));
690 ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_FENCE_UNREF,
807 (void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_SHADER,
1033 ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_GET_3D_CAP
[all...] |
| /external/libdrm/freedreno/kgsl/ |
| kgsl_bo.c | 40 return drmCommandWrite(dev->fd, DRM_KGSL_GEM_SETMEMTYPE,
283 ret = drmCommandWrite(bo->dev->fd, DRM_KGSL_GEM_SET_ACTIVE,
|
| /external/libdrm/libkms/ |
| vmwgfx.c | 178 drmCommandWrite(bo->base.kms->fd, DRM_VMW_UNREF_DMABUF, &arg, sizeof(arg));
|
| /external/libdrm/radeon/ |
| radeon_bo_gem.c | 211 ret = drmCommandWrite(boi->bom->fd, DRM_RADEON_GEM_WAIT_IDLE,
|
| /external/libdrm/ |
| xf86drm.h | 594 extern int drmCommandWrite(int fd, unsigned long drmCommandIndex,
[all...] |
| xf86drm.c | [all...] |
| /external/libdrm/intel/ |
| intel_bufmgr_fake.c | 380 ret = drmCommandWrite(bufmgr_fake->fd, DRM_I915_IRQ_WAIT,
[all...] |
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_bo.c | 101 while (drmCommandWrite(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
[all...] |
