| /external/mesa3d/src/intel/compiler/ |
| test_vec4_register_coalesce.cpp | 60 virtual dst_reg *make_reg_for_system_value(int location)
130 dst_reg temp = dst_reg(v, glsl_type::float_type);
131 dst_reg init;
133 dst_reg m0 = dst_reg(MRF, 0);
149 dst_reg temp = dst_reg(v, glsl_type::vec4_type);
150 dst_reg init;
152 dst_reg m0 = dst_reg(MRF, 0)
[all...] |
| brw_vec4_vs.h | 47 virtual void emit_urb_slot(dst_reg reg, int varying);
53 void emit_clip_distances(dst_reg reg, int offset);
|
| brw_vec4.h | 76 dst_reg dst_null_f()
78 return dst_reg(brw_null_reg());
81 dst_reg dst_null_df()
83 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
86 dst_reg dst_null_d()
88 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
91 dst_reg dst_null_ud()
93 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
113 dst_reg userplane[MAX_CLIP_PLANES];
120 dst_reg output_reg[VARYING_SLOT_TESS_MAX][4]
[all...] |
| test_vec4_copy_propagation.cpp | 57 virtual dst_reg *make_reg_for_system_value(int location)
126 dst_reg a = dst_reg(v, glsl_type::vec4_type);
127 dst_reg b = dst_reg(v, glsl_type::vec4_type);
128 dst_reg c = dst_reg(v, glsl_type::vec4_type);
155 dst_reg a = dst_reg(v, glsl_type::vec4_type);
156 dst_reg b = dst_reg(v, glsl_type::vec4_type)
[all...] |
| brw_ir_vec4.h | 32 class dst_reg;
50 explicit src_reg(const dst_reg ®);
149 class dst_reg : public backend_reg class in namespace:brw
152 DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
156 dst_reg();
157 dst_reg(enum brw_reg_file file, int nr);
158 dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
160 dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
162 dst_reg(struct ::brw_reg reg);
163 dst_reg(class vec4_visitor *v, const struct glsl_type *type)
[all...] |
| brw_vec4_visitor.cpp | 30 vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
88 vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
96 vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
103 vec4_visitor::emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0)
109 vec4_visitor::emit(enum opcode opcode, const dst_reg &dst)
117 return emit(new(mem_ctx) vec4_instruction(opcode, dst_reg()));
122 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
129 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
138 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
149 vec4_visitor::op(const dst_reg &dst, const src_reg &src0,
709 dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) function in class:brw::dst_reg
[all...] |
| gen6_gs_visitor.cpp | 69 emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
74 vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1),
91 emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(URB_WRITE_PRIM_START)));
97 emit(MOV(dst_reg(this->prim_count), brw_imm_ud(0u)));
108 emit(MOV(dst_reg(this->max_svbi),
135 emit(GS_OPCODE_SET_PRIMITIVE_ID, dst_reg(this->primitive_id));
148 dst_reg dst(this->vertex_output);
164 dst_reg tmp = dst_reg(src_reg(this, glsl_type::uvec4_type));
166 dst_reg dst(this->vertex_output)
[all...] |
| brw_fs_builder.h | 46 typedef fs_reg dst_reg; typedef in class:brw::fs_builder
184 dst_reg
190 return dst_reg(VGRF, shader->alloc.allocate(
201 dst_reg
204 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
207 dst_reg
210 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
216 dst_reg
219 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
225 dst_reg
[all...] |
| brw_vec4_builder.h | 46 typedef brw::dst_reg dst_reg; typedef in class:brw::vec4_builder
171 dst_reg
177 return retype(dst_reg(VGRF, shader->alloc.allocate(
187 dst_reg
190 return dst_reg(retype(brw_null_vec(dispatch_width()),
197 dst_reg
200 return dst_reg(retype(brw_null_vec(dispatch_width()),
207 dst_reg
210 return dst_reg(retype(brw_null_vec(dispatch_width())
[all...] |
| brw_vec4_tcs.cpp | 79 emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
117 dst_reg header = dst_reg(this, glsl_type::uvec4_type);
139 dst_reg header(this, glsl_type::uvec4_type);
156 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
163 dst_reg temp(this, glsl_type::ivec4_type);
167 dst_reg header = dst_reg(this, glsl_type::uvec4_type);
192 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
200 dst_reg header = dst_reg(this, glsl_type::uvec4_type)
[all...] |
| brw_vec4_tcs.h | 58 void emit_input_urb_read(const dst_reg &dst,
63 void emit_output_urb_read(const dst_reg &dst,
|
| test_vec4_cmod_propagation.cpp | 60 virtual dst_reg *make_reg_for_system_value(int location)
146 dst_reg dest = dst_reg(v, glsl_type::float_type);
150 dst_reg dest_null = bld.null_reg_f();
182 dst_reg dest = dst_reg(v, glsl_type::float_type);
186 dst_reg dest_null = bld.null_reg_f();
219 dst_reg dest = dst_reg(v, glsl_type::int_type);
255 dst_reg dest = dst_reg(v, glsl_type::uint_type)
[all...] |
| brw_vec4_vs_visitor.cpp | 64 vec4_vs_visitor::emit_urb_slot(dst_reg reg, int varying)
90 vec4_vs_visitor::emit_clip_distances(dst_reg reg, int offset)
130 this->userplane[i] = dst_reg(UNIFORM, this->uniforms);
151 dst_reg(this, glsl_type::vec4_type);
153 dst_reg(this, glsl_type::vec4_type);
|
| brw_vec4_nir.cpp | 57 nir_locals = ralloc_array(mem_ctx, dst_reg, impl->reg_alloc);
59 nir_locals[i] = dst_reg();
66 nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(num_regs));
72 nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);
177 static dst_reg
181 dst_reg reg;
196 dst_reg
200 dst_reg dst =
201 dst_reg(VGRF, alloc.allocate(DIV_ROUND_UP(dest.ssa.bit_size, 32)));
212 dst_reg
[all...] |
| brw_vec4_gs_visitor.cpp | 167 dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
176 inst = emit(MOV(dst_reg(this->vertex_count), brw_imm_ud(0u)));
191 inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
235 dst_reg mrf_reg(MRF, base_mrf);
260 dst_reg mrf_reg(MRF, mrf);
346 emit(ADD(dst_reg(prev_count), this->vertex_count,
350 emit(SHR(dst_reg(dword_index), prev_count,
358 dst_reg mrf_reg(MRF, base_mrf);
368 emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u)));
382 inst = emit(AND(dst_reg(channel), dword_index, brw_imm_ud(3u)))
[all...] |
| brw_vec4_tes.cpp | 107 emit(TES_OPCODE_CREATE_INPUT_READ_HEADER, dst_reg(input_read_header));
189 emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
214 dst_reg temp(this, glsl_type::ivec4_type);
226 dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
233 dst_reg temp(this, glsl_type::dvec4_type);
234 dst_reg temp_d = retype(temp, BRW_REGISTER_TYPE_D);
251 dst_reg shuffled(this, glsl_type::dvec4_type);
254 dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF);
|
| brw_vec4_gs_nir.cpp | 36 dst_reg dest;
54 dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
|
| brw_fs_register_coalesce.cpp | 161 int src_reg = -1, dst_reg = -1; local
186 dst_reg = inst->dst.nr;
189 if (dst_reg != inst->dst.nr)
228 dst_var[i] = live_intervals->var_from_vgrf[dst_reg] + dst_reg_offset[i];
258 scan_inst->dst.nr = dst_reg;
266 scan_inst->src[j].nr = dst_reg;
|
| brw_vec4_surface_builder.cpp | 41 const dst_reg dst = bld.vgrf(src.type,
70 const dst_reg tmp = bld.vgrf(src.type);
123 const dst_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, sz);
144 const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz);
213 const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD);
241 const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
321 const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD);
|
| /external/iproute2/include/ |
| bpf_util.h | 68 /* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */
73 .dst_reg = DST, \
81 .dst_reg = DST, \
86 /* ALU ops on immediates, bpf_add|sub|...: dst_reg += imm32 */
91 .dst_reg = DST, \
99 .dst_reg = DST, \
104 /* Short form of mov, dst_reg = src_reg */
109 .dst_reg = DST, \
117 .dst_reg = DST, \
122 /* Short form of mov, dst_reg = imm32 *
[all...] |
| /external/bcc/src/cc/ |
| libbpf.h | 125 /* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */
130 .dst_reg = DST, \
138 .dst_reg = DST, \
143 /* ALU ops on immediates, bpf_add|sub|...: dst_reg += imm32 */
148 .dst_reg = DST, \
156 .dst_reg = DST, \
161 /* Short form of mov, dst_reg = src_reg */
166 .dst_reg = DST, \
171 /* Short form of mov, dst_reg = imm32 */
176 .dst_reg = DST,
[all...] |
| /external/u-boot/board/gdsys/a38x/ |
| hre.c | 340 static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg,
346 if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid)
348 if (find_key(src_reg->digest, dst_reg->digest, &parent_handle))
374 struct h_reg *src_reg, *dst_reg; local
400 dst_reg = access_hreg(dst_spec, (opcode & 0x40) ? HREG_RDWR : HREG_WR);
430 if (!dst_reg)
451 bin_func(dst_reg->digest, src_buf, 20);
452 dst_reg->valid = true;
456 if (hre_op_loadkey(src_reg, dst_reg, data, data_size)
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| ir-a2xx.c | 283 struct ir2_register *dst_reg = instr->regs[reg++]; local
288 reg_update_stats(dst_reg, info, true);
303 vtx->dst_reg = dst_reg->num;
304 vtx->dst_swiz = reg_fetch_dst_swiz(dst_reg);
331 tex->dst_reg = dst_reg->num;
332 tex->dst_swiz = reg_fetch_dst_swiz(dst_reg);
367 struct ir2_register *dst_reg = instr->regs[reg++]; local
395 reg_update_stats(dst_reg, info, true)
[all...] |
| /external/mesa3d/src/mesa/program/ |
| ir_to_mesa.cpp | 62 class dst_reg;
91 explicit src_reg(dst_reg reg);
101 class dst_reg { class in namespace:__anon34428
103 dst_reg(gl_register_file file, int writemask) function in class:__anon34428::dst_reg
111 dst_reg() function in class:__anon34428::dst_reg
119 explicit dst_reg(src_reg reg);
130 src_reg::src_reg(dst_reg reg)
139 dst_reg::dst_reg(src_reg reg) function in class:dst_reg
154 dst_reg dst
[all...] |
| /external/strace/tests/ |
| bpf-obj_get_info_by_fd.c | 74 uint8_t dst_reg:4; member in struct:bpf_insn
117 .dst_reg = BPF_REG_1,
122 .dst_reg = BPF_REG_10,
128 .dst_reg = BPF_REG_2,
133 .dst_reg = BPF_REG_2,
138 .dst_reg = BPF_REG_1,
151 .dst_reg = BPF_REG_0,
162 ", dst_reg=BPF_REG_1, src_reg=BPF_REG_0, off=0, imm=0}"
164 ", dst_reg=BPF_REG_10, src_reg=BPF_REG_1, off=-4, imm=0}"
166 ", dst_reg=BPF_REG_2, src_reg=BPF_REG_10, off=0, imm=0}
[all...] |
