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    Searched refs:effective_cs (Results 1 - 7 of 7) sorted by null

  /external/u-boot/drivers/ddr/marvell/a38x/
ddr3_training_leveling.h 12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
ddr3_training_leveling.c 77 for (effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++)
80 rl_values[effective_cs][bus_num][if_id] = 0;
82 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
118 effective_cs, STRESS_NONE, DURATION_SINGLE));
139 (0x301b01 | effective_cs << 2), 0x3c3fef));
239 if_id, effective_cs, bus_num))
    [all...]
ddr3_training_pbs.c 70 CRX_PHY_REG(effective_cs) :
71 CTX_PHY_REG(effective_cs);
184 (0x54 + effective_cs * 0x10) :
185 (0x14 + effective_cs * 0x10);
191 (0x55 + effective_cs * 0x10) :
192 (0x15 + effective_cs * 0x10);
244 (0x54 + effective_cs * 0x10) :
245 (0x14 + effective_cs * 0x10);
254 (0x55 + effective_cs * 0x10) :
255 (0x15 + effective_cs * 0x10)
    [all...]
ddr3_training.c 58 u32 effective_cs = 0; variable
    [all...]
ddr3_training_centralization.c 93 reg_phy_off = CTX_PHY_REG(effective_cs);
97 reg_phy_off = CRX_PHY_REG(effective_cs);
188 effective_cs, pattern_id,
441 effective_cs, &reg);
455 effective_cs, reg));
511 if ((ddr3_tip_special_rx_run_once_flag & (1 << effective_cs)) == (1 << effective_cs))
514 ddr3_tip_special_rx_run_once_flag |= (1 << effective_cs);
626 PBS_RX_PHY_REG(effective_cs, pad_num),
636 PBS_RX_PHY_REG(effective_cs, pad_num)
    [all...]
ddr3_training_ip_engine.c 383 (0x3 | (effective_cs << 26)), 0xc000003));
407 delay_between_burst, rd_mode, effective_cs, STRESS_NONE,
459 reg_data = PBS_RX_BCAST_PHY_REG(effective_cs);
462 reg_data = PBS_TX_BCAST_PHY_REG(effective_cs);
473 reg_data = CTX_PHY_REG(effective_cs);
477 reg_data = CRX_PHY_REG(effective_cs);
    [all...]
ddr3_init.h 129 extern u32 effective_cs;

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