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    Searched refs:getPhysRegClass (Results 1 - 15 of 15) sorted by null

  /external/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h 90 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
107 RC = getPhysRegClass(Reg);
SIFixSGPRCopies.cpp 138 TRI.getPhysRegClass(SrcReg);
146 TRI.getPhysRegClass(DstReg);
SIFoldOperands.cpp 213 TRI.getPhysRegClass(UseReg);
241 TRI.getPhysRegClass(DestReg);
SIShrinkInstructions.cpp 77 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
SIRegisterInfo.cpp 680 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
880 const TargetRegisterClass *RC = getPhysRegClass(Reg);
    [all...]
SIWholeQuadMode.cpp 184 TRI->hasVGPRs(TRI->getPhysRegClass(Reg))) {
SILowerControlFlow.cpp 604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg);
605 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg);
SIInstrInfo.cpp     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h 129 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
146 RC = getPhysRegClass(Reg);
SIFixSGPRCopies.cpp 170 TRI.getPhysRegClass(SrcReg);
178 TRI.getPhysRegClass(DstReg);
SIRegisterInfo.cpp 687 const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
858 const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
    [all...]
SIFoldOperands.cpp 372 TRI->getPhysRegClass(DestReg);
412 TRI->getPhysRegClass(UseReg);
    [all...]
SIWholeQuadMode.cpp 389 TRI->hasVGPRs(TRI->getPhysRegClass(Reg))) {
SIInstrInfo.cpp 497 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
571 if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) {
    [all...]
AMDGPUISelDAGToDAG.cpp 320 return TRI->getPhysRegClass(Reg);
    [all...]

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