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Searched
refs:getRawAllocationOrder
(Results
1 - 20
of
20
) sorted by null
/external/swiftshader/third_party/LLVM/lib/CodeGen/
AllocationOrder.cpp
45
TRI.
getRawAllocationOrder
(RC, HintPair.first, Hint,
RegisterClassInfo.cpp
84
ArrayRef<unsigned> RawOrder = RC->
getRawAllocationOrder
(*MF);
RegAllocPBQP.cpp
227
ArrayRef<unsigned> rawOrder = trc->
getRawAllocationOrder
(*mf);
587
physReg = liRC->
getRawAllocationOrder
(*mf).front();
RenderMachineFunction.cpp
437
unsigned capacity = trc->
getRawAllocationOrder
(*mf).size();
484
if (trc->
getRawAllocationOrder
(*mf).empty())
[
all
...]
RegAllocLinearScan.cpp
[
all
...]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
TargetRegisterInfo.h
185
///
getRawAllocationOrder
- Returns the preferred order for allocating
200
ArrayRef<unsigned>
getRawAllocationOrder
(const MachineFunction &MF) const {
505
///
getRawAllocationOrder
- Returns the register allocation order for a
512
getRawAllocationOrder
(const TargetRegisterClass *RC,
515
return RC->
getRawAllocationOrder
(MF);
/external/swiftshader/third_party/LLVM/lib/Target/
TargetRegisterInfo.cpp
76
ArrayRef<unsigned> Order = RC->
getRawAllocationOrder
(MF);
/external/llvm/lib/CodeGen/
RegisterClassInfo.cpp
97
ArrayRef<MCPhysReg> RawOrder = RC->
getRawAllocationOrder
(*MF);
TargetRegisterInfo.cpp
150
ArrayRef<MCPhysReg> Order = RC->
getRawAllocationOrder
(MF);
RegAllocPBQP.cpp
585
ArrayRef<MCPhysReg> RawPRegOrder = TRC->
getRawAllocationOrder
(MF);
717
PReg = RC.
getRawAllocationOrder
(MF).front();
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMBaseRegisterInfo.h
128
ArrayRef<unsigned>
getRawAllocationOrder
(const TargetRegisterClass *RC,
ARMBaseRegisterInfo.cpp
417
///
getRawAllocationOrder
- Returns the register allocation order for a
420
ARMBaseRegisterInfo::
getRawAllocationOrder
(const TargetRegisterClass *RC,
499
return RC->
getRawAllocationOrder
(MF);
505
return RC->
getRawAllocationOrder
(MF);
527
return RC->
getRawAllocationOrder
(MF);
546
return RC->
getRawAllocationOrder
(MF);
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
RegisterClassInfo.cpp
109
ArrayRef<MCPhysReg> RawOrder = RC->
getRawAllocationOrder
(*MF);
TargetRegisterInfo.cpp
212
ArrayRef<MCPhysReg> Order = RC->
getRawAllocationOrder
(MF);
RegAllocPBQP.cpp
613
ArrayRef<MCPhysReg> RawPRegOrder = TRC->
getRawAllocationOrder
(MF);
758
const ArrayRef<MCPhysReg> RawPRegOrder = RC.
getRawAllocationOrder
(MF);
[
all
...]
RegisterScavenging.cpp
585
ArrayRef<MCPhysReg> AllocationOrder = RC.
getRawAllocationOrder
(MF);
/external/llvm/include/llvm/Target/
TargetRegisterInfo.h
224
ArrayRef<MCPhysReg>
getRawAllocationOrder
(const MachineFunction &MF) const {
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
TargetRegisterInfo.h
188
ArrayRef<MCPhysReg>
getRawAllocationOrder
(const MachineFunction &MF) const {
[
all
...]
/external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp
[
all
...]
Completed in 562 milliseconds