| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| RDFRegisters.cpp | 245 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
260 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
275 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
326 for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); ++R)
327 for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); S.isValid(); ++S)
335 BitVector Regs(PRI.getTRI().getNumRegs());
342 BitVector AR(PRI.getTRI().getNumRegs());
357 for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
368 OS << ' ' << printRegUnit(U, &PRI.getTRI());
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| RDFCopy.cpp | 51 const TargetRegisterInfo &TRI = DFG.getTRI();
123 const TargetRegisterInfo &TRI = DFG.getTRI();
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| RDFRegisters.h | 133 const TargetRegisterInfo &getTRI() const { return TRI; }
160 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
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| RDFLiveness.h | 56 : DFG(g), TRI(g.getTRI()), PRI(g.getPRI()), MDT(g.getDT()),
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| RDFDeadCode.cpp | 71 for (unsigned R = 0, RN = DFG.getTRI().getNumRegs(); R != RN; ++R) {
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| RDFGraph.h | 664 const TargetRegisterInfo &getTRI() const { return TRI; }
[all...] |
| RDFLiveness.cpp | 65 OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{';
[all...] |
| RDFGraph.cpp | 60 auto &TRI = P.G.getTRI();
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| RDFLiveness.h | 37 : DFG(g), TRI(g.getTRI()), MDT(g.getDT()), MDF(g.getDF()),
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| RDFCopy.cpp | 46 const TargetRegisterInfo &TRI = DFG.getTRI();
65 unsigned S = DFG.getTRI().composeSubRegIndices(DefR.Sub, I.SubIdx);
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| RDFGraph.h | 621 const TargetRegisterInfo &getTRI() const {
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| RDFGraph.cpp | 33 auto &TRI = P.G.getTRI();
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIMachineScheduler.h | 452 const TargetRegisterInfo *getTRI() { return TRI; }
|
| SIMachineScheduler.cpp | 571 dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
575 dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIMachineScheduler.h | 461 const TargetRegisterInfo *getTRI() { return TRI; }
|
| SIMachineScheduler.cpp | 605 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
609 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
[all...] |
