| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| flat.s | 23 flat_load_dword v1, v[3:4] glc
25 // CI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
26 // VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
28 flat_load_dword v1, v[3:4] glc slc
30 // CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
31 // VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
37 flat_store_dword v[3:4], v1 glc
39 // CIVI: flat_store_dword v[3:4], v1 glc ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x00,0x00]
41 flat_store_dword v[3:4], v1 glc slc
43 // CIVI: flat_store_dword v[3:4], v1 glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00
[all...] |
| smem.s | 59 s_store_dword s1, s[2:3], 0xfc glc
60 // GFX89: s_store_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x43,0xc0,0xfc,0x00,0x00,0x00]
67 s_store_dword s1, s[2:3], s4 glc
68 // GFX89: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
91 // FIXME: Should error on SI instead of silently ignoring glc
92 s_load_dword s1, s[2:3], 0xfc glc
93 // GFX89: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
95 s_load_dword s1, s[2:3], s4 glc
96 // GFX89: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
131 s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc
[all...] |
| mubuf.s | 29 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc
30 // SICI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0x01,0x01]
31 // VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x01,0x01,0x01]
41 buffer_load_dword v1, off, s[4:7], s1 glc tfe
42 // SICI: buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x30,0xe0,0x00,0x01,0x81,0x01]
43 // VI: buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x50,0xe0,0x00,0x01,0x81,0x01]
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
46 // SICI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01]
47 // VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x81,0x01]
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tf
[all...] |
| flat-gfx9.s | 22 flat_load_dword v1, v[3:4] offset:4 glc
23 // GFX9: flat_load_dword v1, v[3:4] offset:4 glc ; encoding: [0x04,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
26 flat_load_dword v1, v[3:4] offset:4 glc slc
27 // GFX9: flat_load_dword v1, v[3:4] offset:4 glc slc ; encoding: [0x04,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
54 flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 glc
57 flat_atomic_cmpswap v[1:2], v[3:4] glc
60 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
61 // GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc ; encoding: [0xff,0x0f,0x05,0xdd,0x01,0x03,0x00,0x00]
64 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc
65 // GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc ; encoding: [0xff,0x0f,0x07,0xdd,0x01,0x03,0x00,0x00
[all...] |
| mimg.s | 39 image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
41 // VI: image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
72 image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16
74 // VI: image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16 ; encoding: [0x00,0xf1,0x22,0xf2,0x01,0x05,0x02,0x80]
179 image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da
180 // GCN: image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da ; encoding: [0x00,0x71,0x13,0xf2,0x01,0x05,0x02,0x00]
185 image_load_pck v5, v[1:4], s[8:15] dmask:0x1 glc
186 // GCN: image_load_pck v5, v[1:4], s[8:15] dmask:0x1 glc ; encoding: [0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00]
208 image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da
209 // GCN: image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da ; encoding: [0x00,0x71,0x2e,0xf2,0x02,0x01,0x03,0x00
[all...] |
| mubuf-gfx9.s | 52 buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc
53 // GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x98,0xe0,0x00,0x05,0x02,0x03]
76 buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc
77 // GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04]
|
| trap.s | 248 buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
249 // SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
250 // VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
251 // GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
255 buffer_atomic_inc v1, off, ttmp[12:15], 56 glc
257 // GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
|
| gfx9_asm_all.s | [all...] |
| gfx8_asm_all.s | [all...] |
| gfx7_asm_all.s | [all...] |
| /external/llvm/test/MC/AMDGPU/ |
| flat.s | 23 flat_load_dword v1, v[3:4] glc
25 // CI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
26 // VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
28 flat_load_dword v1, v[3:4] glc slc
30 // CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
31 // VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
33 flat_load_dword v1, v[3:4] glc tfe
35 // CI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
36 // VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
38 flat_load_dword v1, v[3:4] glc slc tf
[all...] |
| mimg.s | 17 image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc
18 // SICI: image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0xc0,0x07,0x00]
19 // VI : image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
21 image_atomic_swap v4, v[192:195], s[28:35] dmask:0x1 unorm glc
22 // SICI: image_atomic_swap v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0xc0,0xc0,0x07,0x00]
23 // VI : image_atomic_swap v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0xc0,0x04,0x07,0x00]
25 image_atomic_cmpswap v[4:5], v[192:195], s[28:35] dmask:0x1 unorm glc
26 // SIIC: image_atomic_cmpswap v[4:5], v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0xc0,0xc0,0x07,0x00]
27 // VI : image_atomic_cmpswap v[4:5], v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0xc0,0x07,0x00]
|
| mubuf.s | 29 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc
30 // SICI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0x01,0x01]
31 // VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x01,0x01,0x01]
41 buffer_load_dword v1, off, s[4:7], s1 glc tfe
42 // SICI: buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x30,0xe0,0x00,0x01,0x81,0x01]
43 // VI: buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x50,0xe0,0x00,0x01,0x81,0x01]
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
46 // SICI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01]
47 // VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x81,0x01]
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tf
[all...] |
| trap.s | 142 buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
143 // SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
144 // VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
|
| /external/mesa3d/src/amd/common/ |
| ac_llvm_build.h | 205 bool glc,
217 unsigned glc,
|
| ac_llvm_build.c | 844 bool glc,
866 soffset, inst_offset, glc, slc,
870 glc, slc,
891 LLVMConstInt(ctx->i1, glc, 0),
925 LLVMConstInt(ctx->i32, glc, 0),
952 unsigned glc,
963 /* TODO: VI and later generations can use SMEM with GLC=1.*/
964 if (allow_smem && !glc && !slc) {
994 LLVMConstInt(ctx->i1, glc, 0),
1021 ctx->i1false, /* glc */
[all...] |
| ac_nir_to_llvm.c | 3671 LLVMValueRef glc = ctx->ac.i1false; local
3709 LLVMValueRef glc = ctx->ac.i1false; local
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SILoadStoreOptimizer.cpp | 436 CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm();
437 CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm();
654 .addImm(CI.GLC0) // glc
711 .addImm(CI.GLC0) // glc
814 .addImm(CI.GLC0) // glc
[all...] |
| SIMemoryLegalizer.cpp | 311 /// Sets GLC bit to "true" if present in \p MI. Returns true if \p MI
314 return enableNamedBit<AMDGPU::OpName::glc>(MI);
630 /// TODO: Do not set glc for rmw atomic operations as they
[all...] |
| SIInstrInfo.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader_tgsi_mem.c | 292 LLVMValueRef glc = local
303 emit_data->args[emit_data->arg_count++] = glc;
310 emit_data->args[emit_data->arg_count++] = glc;
343 i1true : i1false; /* glc */
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | [all...] |
