1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * NVIDIA Tegra20 GPIO handling. 4 * (C) Copyright 2010-2012,2015 5 * NVIDIA Corporation <www.nvidia.com> 6 */ 7 8 /* 9 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. 10 * Tom Warren (twarren (at) nvidia.com) 11 */ 12 13 #include <common.h> 14 #include <dm.h> 15 #include <malloc.h> 16 #include <errno.h> 17 #include <fdtdec.h> 18 #include <asm/io.h> 19 #include <asm/bitops.h> 20 #include <asm/arch/tegra.h> 21 #include <asm/gpio.h> 22 #include <dm/device-internal.h> 23 #include <dt-bindings/gpio/gpio.h> 24 25 static const int CONFIG_SFIO = 0; 26 static const int CONFIG_GPIO = 1; 27 static const int DIRECTION_INPUT = 0; 28 static const int DIRECTION_OUTPUT = 1; 29 30 struct tegra_gpio_platdata { 31 struct gpio_ctlr_bank *bank; 32 const char *port_name; /* Name of port, e.g. "B" */ 33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 34 }; 35 36 /* Information about each port at run-time */ 37 struct tegra_port_info { 38 struct gpio_ctlr_bank *bank; 39 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 40 }; 41 42 /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */ 43 static int get_config(unsigned gpio) 44 { 45 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 46 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 47 u32 u; 48 int type; 49 50 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 51 type = (u >> GPIO_BIT(gpio)) & 1; 52 53 debug("get_config: port = %d, bit = %d is %s\n", 54 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 55 56 return type ? CONFIG_GPIO : CONFIG_SFIO; 57 } 58 59 /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */ 60 static void set_config(unsigned gpio, int type) 61 { 62 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 63 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 64 u32 u; 65 66 debug("set_config: port = %d, bit = %d, %s\n", 67 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 68 69 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 70 if (type != CONFIG_SFIO) 71 u |= 1 << GPIO_BIT(gpio); 72 else 73 u &= ~(1 << GPIO_BIT(gpio)); 74 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); 75 } 76 77 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ 78 static int get_direction(unsigned gpio) 79 { 80 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 81 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 82 u32 u; 83 int dir; 84 85 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 86 dir = (u >> GPIO_BIT(gpio)) & 1; 87 88 debug("get_direction: port = %d, bit = %d, %s\n", 89 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); 90 91 return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT; 92 } 93 94 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ 95 static void set_direction(unsigned gpio, int output) 96 { 97 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 98 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 99 u32 u; 100 101 debug("set_direction: port = %d, bit = %d, %s\n", 102 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); 103 104 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 105 if (output != DIRECTION_INPUT) 106 u |= 1 << GPIO_BIT(gpio); 107 else 108 u &= ~(1 << GPIO_BIT(gpio)); 109 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); 110 } 111 112 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ 113 static void set_level(unsigned gpio, int high) 114 { 115 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 116 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 117 u32 u; 118 119 debug("set_level: port = %d, bit %d == %d\n", 120 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); 121 122 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); 123 if (high) 124 u |= 1 << GPIO_BIT(gpio); 125 else 126 u &= ~(1 << GPIO_BIT(gpio)); 127 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); 128 } 129 130 /* 131 * Generic_GPIO primitives. 132 */ 133 134 /* set GPIO pin 'gpio' as an input */ 135 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) 136 { 137 struct tegra_port_info *state = dev_get_priv(dev); 138 139 /* Configure GPIO direction as input. */ 140 set_direction(state->base_gpio + offset, DIRECTION_INPUT); 141 142 /* Enable the pin as a GPIO */ 143 set_config(state->base_gpio + offset, 1); 144 145 return 0; 146 } 147 148 /* set GPIO pin 'gpio' as an output, with polarity 'value' */ 149 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, 150 int value) 151 { 152 struct tegra_port_info *state = dev_get_priv(dev); 153 int gpio = state->base_gpio + offset; 154 155 /* Configure GPIO output value. */ 156 set_level(gpio, value); 157 158 /* Configure GPIO direction as output. */ 159 set_direction(gpio, DIRECTION_OUTPUT); 160 161 /* Enable the pin as a GPIO */ 162 set_config(state->base_gpio + offset, 1); 163 164 return 0; 165 } 166 167 /* read GPIO IN value of pin 'gpio' */ 168 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) 169 { 170 struct tegra_port_info *state = dev_get_priv(dev); 171 int gpio = state->base_gpio + offset; 172 int val; 173 174 debug("%s: pin = %d (port %d:bit %d)\n", __func__, 175 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); 176 177 if (get_direction(gpio) == DIRECTION_INPUT) 178 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); 179 else 180 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]); 181 182 return (val >> GPIO_BIT(gpio)) & 1; 183 } 184 185 /* write GPIO OUT value to pin 'gpio' */ 186 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value) 187 { 188 struct tegra_port_info *state = dev_get_priv(dev); 189 int gpio = state->base_gpio + offset; 190 191 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", 192 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); 193 194 /* Configure GPIO output value. */ 195 set_level(gpio, value); 196 197 return 0; 198 } 199 200 void gpio_config_table(const struct tegra_gpio_config *config, int len) 201 { 202 int i; 203 204 for (i = 0; i < len; i++) { 205 switch (config[i].init) { 206 case TEGRA_GPIO_INIT_IN: 207 set_direction(config[i].gpio, DIRECTION_INPUT); 208 break; 209 case TEGRA_GPIO_INIT_OUT0: 210 set_level(config[i].gpio, 0); 211 set_direction(config[i].gpio, DIRECTION_OUTPUT); 212 break; 213 case TEGRA_GPIO_INIT_OUT1: 214 set_level(config[i].gpio, 1); 215 set_direction(config[i].gpio, DIRECTION_OUTPUT); 216 break; 217 } 218 set_config(config[i].gpio, CONFIG_GPIO); 219 } 220 } 221 222 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset) 223 { 224 struct tegra_port_info *state = dev_get_priv(dev); 225 int gpio = state->base_gpio + offset; 226 227 if (!get_config(gpio)) 228 return GPIOF_FUNC; 229 else if (get_direction(gpio)) 230 return GPIOF_OUTPUT; 231 else 232 return GPIOF_INPUT; 233 } 234 235 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, 236 struct ofnode_phandle_args *args) 237 { 238 int gpio, port, ret; 239 240 gpio = args->args[0]; 241 port = gpio / TEGRA_GPIOS_PER_PORT; 242 ret = device_get_child(dev, port, &desc->dev); 243 if (ret) 244 return ret; 245 desc->offset = gpio % TEGRA_GPIOS_PER_PORT; 246 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; 247 248 return 0; 249 } 250 251 static const struct dm_gpio_ops gpio_tegra_ops = { 252 .direction_input = tegra_gpio_direction_input, 253 .direction_output = tegra_gpio_direction_output, 254 .get_value = tegra_gpio_get_value, 255 .set_value = tegra_gpio_set_value, 256 .get_function = tegra_gpio_get_function, 257 .xlate = tegra_gpio_xlate, 258 }; 259 260 /** 261 * Returns the name of a GPIO port 262 * 263 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ... 264 * 265 * @base_port: Base port number (0, 1..n-1) 266 * @return allocated string containing the name 267 */ 268 static char *gpio_port_name(int base_port) 269 { 270 char *name, *s; 271 272 name = malloc(3); 273 if (name) { 274 s = name; 275 *s++ = 'A' + (base_port % 26); 276 if (base_port >= 26) 277 *s++ = *name; 278 *s = '\0'; 279 } 280 281 return name; 282 } 283 284 static const struct udevice_id tegra_gpio_ids[] = { 285 { .compatible = "nvidia,tegra30-gpio" }, 286 { .compatible = "nvidia,tegra20-gpio" }, 287 { } 288 }; 289 290 static int gpio_tegra_probe(struct udevice *dev) 291 { 292 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 293 struct tegra_port_info *priv = dev->priv; 294 struct tegra_gpio_platdata *plat = dev->platdata; 295 296 /* Only child devices have ports */ 297 if (!plat) 298 return 0; 299 300 priv->bank = plat->bank; 301 priv->base_gpio = plat->base_gpio; 302 303 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; 304 uc_priv->bank_name = plat->port_name; 305 306 return 0; 307 } 308 309 /** 310 * We have a top-level GPIO device with no actual GPIOs. It has a child 311 * device for each Tegra port. 312 */ 313 static int gpio_tegra_bind(struct udevice *parent) 314 { 315 struct tegra_gpio_platdata *plat = parent->platdata; 316 struct gpio_ctlr *ctlr; 317 int bank_count; 318 int bank; 319 int ret; 320 321 /* If this is a child device, there is nothing to do here */ 322 if (plat) 323 return 0; 324 325 /* TODO(sjg (at) chromium.org): Remove once SPL supports device tree */ 326 #ifdef CONFIG_SPL_BUILD 327 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 328 bank_count = TEGRA_GPIO_BANKS; 329 #else 330 { 331 int len; 332 333 /* 334 * This driver does not make use of interrupts, other than to figure 335 * out the number of GPIO banks 336 */ 337 len = dev_read_size(parent, "interrupts"); 338 if (len < 0) 339 return len; 340 bank_count = len / 3 / sizeof(u32); 341 ctlr = (struct gpio_ctlr *)dev_read_addr(parent); 342 if ((ulong)ctlr == FDT_ADDR_T_NONE) 343 return -EINVAL; 344 } 345 #endif 346 for (bank = 0; bank < bank_count; bank++) { 347 int port; 348 349 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { 350 struct tegra_gpio_platdata *plat; 351 struct udevice *dev; 352 int base_port; 353 354 plat = calloc(1, sizeof(*plat)); 355 if (!plat) 356 return -ENOMEM; 357 plat->bank = &ctlr->gpio_bank[bank]; 358 base_port = bank * TEGRA_PORTS_PER_BANK + port; 359 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; 360 plat->port_name = gpio_port_name(base_port); 361 362 ret = device_bind(parent, parent->driver, 363 plat->port_name, plat, -1, &dev); 364 if (ret) 365 return ret; 366 dev_set_of_offset(dev, dev_of_offset(parent)); 367 } 368 } 369 370 return 0; 371 } 372 373 U_BOOT_DRIVER(gpio_tegra) = { 374 .name = "gpio_tegra", 375 .id = UCLASS_GPIO, 376 .of_match = tegra_gpio_ids, 377 .bind = gpio_tegra_bind, 378 .probe = gpio_tegra_probe, 379 .priv_auto_alloc_size = sizeof(struct tegra_port_info), 380 .ops = &gpio_tegra_ops, 381 .flags = DM_FLAG_PRE_RELOC, 382 }; 383
