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  /external/u-boot/drivers/clk/rockchip/
clk_rv1108.c 202 unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); local
207 printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
clk_rk3368.c 132 u32 apllb, aplll, dpll, cpll, gpll; local
139 * GPLL rate from the SPL stage.
141 rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
149 gpll = rkclk_pll_get_rate(cru, GPLL);
151 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
152 __func__, apllb, aplll, dpll, cpll, gpll);
179 pll_rate = rkclk_pll_get_rate(cru, GPLL);
354 * to select either CPLL or GPLL as the clock-parent. The location within
463 rate = rkclk_pll_get_rate(priv->cru, GPLL);
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