HomeSort by relevance Sort by last modified time
    Searched refs:hasSubClassEq (Results 1 - 25 of 58) sorted by null

1 2 3

  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86RegisterBankInfo.cpp 47 if (X86::GR8RegClass.hasSubClassEq(&RC) ||
48 X86::GR16RegClass.hasSubClassEq(&RC) ||
49 X86::GR32RegClass.hasSubClassEq(&RC) ||
50 X86::GR64RegClass.hasSubClassEq(&RC))
53 if (X86::FR32XRegClass.hasSubClassEq(&RC) ||
54 X86::FR64XRegClass.hasSubClassEq(&RC) ||
55 X86::VR128XRegClass.hasSubClassEq(&RC) ||
56 X86::VR256XRegClass.hasSubClassEq(&RC) ||
57 X86::VR512RegClass.hasSubClassEq(&RC))
X86DomainReassignment.cpp 50 return X86::GR64RegClass.hasSubClassEq(RC) ||
51 X86::GR32RegClass.hasSubClassEq(RC) ||
52 X86::GR16RegClass.hasSubClassEq(RC) ||
53 X86::GR8RegClass.hasSubClassEq(RC);
58 return X86::VK16RegClass.hasSubClassEq(RC);
74 if (X86::GR8RegClass.hasSubClassEq(SrcRC))
76 if (X86::GR16RegClass.hasSubClassEq(SrcRC))
78 if (X86::GR32RegClass.hasSubClassEq(SrcRC))
80 if (X86::GR64RegClass.hasSubClassEq(SrcRC))
  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 192 if (Mips::GPR32RegClass.hasSubClassEq(RC))
194 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
196 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
200 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
204 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
208 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
218 else if (Mips::LO32RegClass.hasSubClassEq(RC)
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 260 if (Mips::GPR32RegClass.hasSubClassEq(RC))
262 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
264 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
266 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
268 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
270 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
272 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
274 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
276 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
289 else if (Mips::LO32RegClass.hasSubClassEq(RC)
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 708 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
709 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
710 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
711 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
742 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
743 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
745 PPC::GPRCRegClass.hasSubClassEq(RC) ||
746 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
    [all...]
PPCVSXCopy.cpp 59 return RC->hasSubClassEq(MRI.getRegClass(Reg));
  /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
PPCInstrInfo.cpp 337 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
353 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
369 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
374 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
379 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
417 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
451 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
502 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
511 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
520 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC))
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
RISCVInstrInfo.cpp 120 if (RISCV::GPRRegClass.hasSubClassEq(RC))
123 else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
125 else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
147 if (RISCV::GPRRegClass.hasSubClassEq(RC))
150 else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
152 else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 763 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
764 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
765 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
766 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
794 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
795 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
797 PPC::GPRCRegClass.hasSubClassEq(RC) ||
798 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
    [all...]
PPCVSXCopy.cpp 59 return RC->hasSubClassEq(MRI.getRegClass(Reg));
  /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
BlackfinISelDAGToDAG.cpp 120 return BF::AnyCCRegClass.hasSubClassEq(RC);
124 return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
BlackfinInstrInfo.cpp 166 return Test.hasSubClassEq(RC);
  /external/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp 42 if (!RC.hasSubClassEq(&SubRC))
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp 47 if (!RC.hasSubClassEq(&SubRC))
  /external/swiftshader/third_party/LLVM/include/llvm/Target/
TargetRegisterInfo.h 143 return RC != this && hasSubClassEq(RC);
146 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
148 bool hasSubClassEq(const TargetRegisterClass *RC) const {
162 return RC->hasSubClassEq(this);
166 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 308 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
382 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
383 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
396 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
397 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
777 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 145 return RC != this && hasSubClassEq(RC);
149 bool hasSubClassEq(const TargetRegisterClass *RC) const {
162 return RC->hasSubClassEq(this);
179 /// See the implementation of hasSubClassEq for an example of how it
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
TargetRegisterInfo.h 111 return RC != this && hasSubClassEq(RC);
115 bool hasSubClassEq(const TargetRegisterClass *RC) const {
128 return RC->hasSubClassEq(this);
145 /// See the implementation of hasSubClassEq for an example of how it
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 426 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
503 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
504 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
517 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
518 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 418 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
421 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
456 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
459 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 422 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
425 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
460 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
463 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
ARCInstrInfo.cpp 299 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
326 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 35 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
39 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 879 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
883 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
887 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
891 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp     [all...]

Completed in 4453 milliseconds

1 2 3