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Searched
refs:hasVGPRs
(Results
1 - 12
of
12
) sorted by null
/external/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp
122
if (TRI->
hasVGPRs
(MRI.getRegClass(MI.getOperand(i).getReg())))
154
return TRI.isSGPRClass(DstRC) && TRI.
hasVGPRs
(SrcRC);
160
return TRI.isSGPRClass(SrcRC) && TRI.
hasVGPRs
(DstRC);
319
if (TRI->
hasVGPRs
(MRI.getRegClass(Reg))) {
344
if (TRI->
hasVGPRs
(TII->getOpRegClass(MI, 0)) ||
361
(TRI->
hasVGPRs
(Src0RC) || TRI->
hasVGPRs
(Src1RC))) {
SIRegisterInfo.h
94
return !
hasVGPRs
(RC);
112
bool
hasVGPRs
(const TargetRegisterClass *RC) const;
SIShrinkInstructions.cpp
75
return TRI.
hasVGPRs
(MRI.getRegClass(MO->getReg()));
77
return TRI.
hasVGPRs
(TRI.getPhysRegClass(MO->getReg()));
SIWholeQuadMode.cpp
184
TRI->
hasVGPRs
(TRI->getPhysRegClass(Reg))) {
SIRegisterInfo.cpp
708
bool SIRegisterInfo::
hasVGPRs
(const TargetRegisterClass *RC) const {
[
all
...]
SIInstrInfo.cpp
620
assert(RI.
hasVGPRs
(RC) && "Only VGPR spilling expected");
714
assert(RI.
hasVGPRs
(RC) && "Only VGPR spilling expected");
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp
154
if (TRI->
hasVGPRs
(MRI.getRegClass(MI.getOperand(i).getReg())))
186
return TRI.isSGPRClass(DstRC) && TRI.
hasVGPRs
(SrcRC);
192
return TRI.isSGPRClass(SrcRC) && TRI.
hasVGPRs
(DstRC);
310
if (TRI->
hasVGPRs
(MRI.getRegClass(Reg)))
685
if (TRI->
hasVGPRs
(TII->getOpRegClass(MI, 0)) ||
701
(TRI->
hasVGPRs
(Src0RC) || TRI->
hasVGPRs
(Src1RC))) {
SIRegisterInfo.h
133
return !
hasVGPRs
(RC);
151
bool
hasVGPRs
(const TargetRegisterClass *RC) const;
SIInstrInfo.cpp
920
assert(RI.
hasVGPRs
(RC) && "Only VGPR spilling expected");
[
all
...]
SIRegisterInfo.cpp
[
all
...]
SIWholeQuadMode.cpp
389
TRI->
hasVGPRs
(TRI->getPhysRegClass(Reg))) {
SIPeepholeSDWA.cpp
[
all
...]
Completed in 182 milliseconds